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| SPANSION Flash Memory Data Sheet TM September 2003 TM This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a SPANSION revisions will occur when appropriate, and changes will be noted in a revision summary. TM product. Future routine Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about SPANSION solutions. TM memory FUJITSU SEMICONDUCTOR DATA SHEET DS05-20909-1E PAGE MODE FLASH MEMORY CMOS 128M (8Mx 16) BIT MBM29QM12DH-60 s DESCRIPTION The MBM29QM12DH is 128 M-bit, 3.0 V-only Page mode and dual operation Flash memory organized as 8M words of 16 bits each. The device is offered in 56-pin TSOP and 80-ball FBGA package. This device is designed to be programmed in-system with the standard system 3.0 V Vcc supply. 12.0 V Vpp and 5.0 V Vcc are not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers. (Continued) s PRODUCT LINE UP Part No. VCC = 3.0 V +0.6 V -0.3 V MBM29QM12DH60 VCCQ = 2.7 V to 3.6 V 60 20 60 20 VCCQ = 1.65 V to 1.95 V 70 30 70 30 Max Random Address Access Time (ns) Max Page Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) s PACKAGES 56-pin plastic TSOP (1) 80-pin plastic FBGA (FPT-56P-M01) (BGA-80P-M04) MBM29QM12DH-60 (Continued) The device provides truly high performance non-volatile Flash memory solution. The device offers fast page access times of 20 ns with random access times of 60 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. The page size is 8 words. The dual operation function provides simultaneous operation by dividing the memory space into four banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank with zero latency. This releases the system from waiting for the completion of program or erase operations. The device is command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal statemachine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The device is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. Typically, each 32K words sector can be programmed and verified in about 0.3 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margins. Any individual sector is typically erased and verified in 0.5 second. (If already preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device is erased when shipped from the factory. The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, output pin. Once the end of a program or erase cycle has been completed, the device internally resets to the read mode. Fujitsu's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The device memory electrically erases all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The words are programmed one word at a time using the EPROM programming mechanism of hot electron injection. 2 MBM29QM12DH-60 s FEATURES * 0.13 m Process Technology * Single 3.0 V read, program and erase Minimized system level power requirements * Simultaneous Read/Write operations (Dual Bank) * FlexBankTM *1 Bank A: 16 Mbit (4 KW x 8 and 32 KW x 31) Bank B: 48 Mbit (32 KW x 96) Bank C: 48 Mbit (32 KW x 96) Bank D: 16 Mbit (4 KW x 8 and 32 KW x 31) * Enhanced VI/O (VCCQ) Feature Input / Output voltage generated on the device is determined based on the VI/O level VI/O (VCCQ) range : 2.7 V to 3.6 V or 1.65 V to 1.95 V * High Performance Page Mode 20 ns maximum page access time (60 ns random access time) (3 V VI/O) * 8 words Page ( x 16) * Compatible with JEDEC-standard commands Uses same software commands as E2PROMs * Minimum 100,000 program/erase cycles * Sector erase architecture Eight 4K words, two hundred fifty-four 32K words, eight 8K words sectors. Any combination of sectors can be concurrently erased. Also supports full chip erase * Dual Boot Block 164K words boot block sectors, 8 at the top of the address range and 8 at the bottom of the address range * HiddenROM region 64 words for factory and 64 words for customer of HiddenROM, accessible through a new "HiddenROM Enable" command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) * WP/ACC input pin At VIL, allows protection of "outermost" 2x4K words on both ends of boot sectors, regardless of sector protection/unprotection status At VIH, allows removal of boot sector protection At VACC, increases program performance * Embedded EraseTM *2 Algorithms Automatically preprograms and erases the chip or any sector * Embedded ProgramTM *2 Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic sleep mode When addresses remain stable, the device automatically switches itself to low power mode. * Low VCC write inhibit 2.5 V (Continued) 3 MBM29QM12DH-60 (Continued) * Program Suspend/Resume Suspends the program operation to allow a read in another byte * Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device * In accordance with CFI (Common Flash Memory Interface) * Hardware Reset Pin (RESET) Hardware method to reset the device for reading array data * New Sector Protection Persistent Sector Protection Password Sector Protection *1 : FlexBankTM is a trademark of Fujitsu Limited, Japan. *2 : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 4 MBM29QM12DH-60 s PIN ASSIGNMENT TSOP (1) (Top View) RESET RY/BY A0 A1 A2 A3 A4 A5 VCC DQ0 DQ1 DQ2 DQ3 VSSQ VCCQ DQ4 DQ5 DQ6 DQ7 VSS N.C. A6 A7 A8 A9 A10 A11 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 (Marking Side) 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 WP/ACC WE N.C. A22 A21 A20 OE N.C. CE VSS DQ15 DQ14 DQ13 DQ12 VSSQ VCCQ DQ11 DQ10 DQ9 DQ8 VCC A19 A18 A17 A16 A15 A14 A13 (FPT-56P-M01) (Continued) 5 MBM29QM12DH-60 (Continued) FBGA (Top View) (Marking Side) A8 N.C. A7 N.C. B8 N.C. B7 N.C. C8 N.C. C7 A13 C6 A9 D8 A22 D7 A12 D6 A8 E8 N.C. E7 A14 E6 A10 F8 VCCQ F7 A15 F6 A11 F5 A19 F4 A20 F3 A5 F2 A1 F1 N.C. G8 VSSQ G7 A16 G6 DQ7 G5 DQ5 G4 DQ2 G3 DQ0 G2 A0 G1 N.C. H8 N.C. H7 N.C. J8 N.C. J7 DQ15 K8 N.C. K7 VSS K6 DQ6 K5 DQ4 K4 DQ3 K3 DQ1 K2 VSS L8 N.C. L7 N.C. M8 N.C. M7 N.C. H6 J6 DQ14 DQ13 H5 DQ12 H4 DQ10 H3 DQ8 H2 CE H1 VCCQ J5 VCC J4 DQ11 J3 DQ9 J2 OE C5 D5 E5 WE RESET A21 C4 D4 E4 RY/BY WP/ACC A18 C3 A7 A2 N.C. A1 N.C. B2 N.C. B1 N.C. C2 A3 C1 N.C. D3 A17 D2 A4 D1 VCC E3 A6 E2 A2 E1 N.C. L2 N.C. L1 N.C. M2 N.C. M1 N.C. J1 K1 VSSQ N.C. (BGA-80P-M04) s PIN DESCRIPTIONS MBM29QM12DH Pin Configuration Table Pin A22 to A0 DQ15 to DQ0 CE OE WE RESET WP/ACC RY/BY N.C. VSS VCC VSSQ VCCQ 6 Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Hardware Reset Hardware Write Protection/ Program Acceleration Ready/Busy output Pin Not Connected Internally Device Ground Device Power Supply Input & Output Buffer Ground Input & Output Buffer Power Supply Function MBM29QM12DH-60 s BLOCK DIAGRAM VCC VSS Y-Gating Cell Matrix 16 Mbit (Bank A) X-Decoder Bank B Address RESET WE CE OE WP/ACC DQ15 to DQ0 State Control & Command Register RY/BY Status Control Bank C Address DQ15 to DQ0 Cell Matrix 48 Mbit (Bank B) X-Decoder Y-Gating Y-Gating Bank A address A22 to A0 X-Decoder Cell Matrix 16 Mbit (Bank D) Y-Gating X-Decoder Cell Matrix 48 Mbit (Bank C) Bank D address s LOGIC SYMBOL 23 A22 to A0 DQ15 to DQ0 RESET CE OE WE WP/ACC RY/BY 16 7 MBM29QM12DH-60 s DEVICE BUS OPERATION MBM29QM12DH User Bus Operations Table Operation Auto-Select Manufacturer Code*1 Auto-Select Device Code*1 Extended Auto-Select Device Code*2 Read*3 Standby Output Disable Write (Program/Erase) Enable Sector Group Protection*3,*4 Verify Sector Group Protection*3,*4 Boot Block Sector Write Protection*6 Temporary Sector Group Unprotection*5 Reset CE OE WE A0 L L L L L H L L L L X X X L L L L L X H H VID L X X X H X X X H H H H H X H L L H L H A0 X X A0 L L X X X A1 L L H H A1 X X A1 H H X X X A2 L L H H A2 X X A2 L L X X X A3 L L H H A3 X X A3 L L X X X A4 X X X X A4 X X A4 L L X X X A5 X X X X A5 X X A5 L L X X X A6 L L L L A6 X X A6 L L X X X A7 L L L L A7 X X A7 L L X X X A9 VID VID VID VID A9 X X A9 VID VID X X X DQ15 to WP/ RESET DQ0 ACC Code Code Code Code DOUT High-Z High-Z DIN X Code X X High-Z H H H H H H H H H H H VID L X X X X X X X X X H L X X Legend: L = VIL, H = VIH, X = VIL or VIH, = Pulse input. See DC Characteristics for voltage levels. *1 : Manufacturer and device codes may also be accessed via a command register write sequence. See "MBM29QM12DH Command Definitions Table" in "s DEVICE BUS OPERATION". *2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *3 : Refer to section on Sector Protection. *4 : VCCQ = 2.7 V to 3.6 V for 60 ns VCCQ = 1.65 V to 1.95 V for 70 ns. *5 : Also used for the extended sector group protection. *6 : Protect "outermost" 2 x 4K words on both ends of the boot block sectors (SA0, SA1, SA268, SA269) . 8 MBM29QM12DH-60 MBM29QM12DH Command Definitions Table Second Seventh Bus First Bus Third Bus Fourth Bus Sixth Bus Bus Fifth Bus Bus Write Write Write Read/Write Write Write Write Cycle Write CyCycle Cycle Cycle Cycle Cycle Cycle cles Req'd Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data 1 3 3 4 6 6 1 1 3 2 2 XXXh F0h Command Sequence Read/Reset Read/Reset Autoselect Program Chip Erase Sector Erase Program/Erase Suspend Program/Erase Resume Set to Fast Mode Fast Program Reset from Fast Mode *1 Extended Sector Group Protection *2 Query HiddenROM Entry HiddenROM Program *3 HiddenROM Exit *3 HiddenROM Protect *3 RA RD -- 555h (BA) 555h 555h 555h 555h -- -- 555h -- -- SGA+ WPH -- F0h 90h A0h -- RA -- PA -- RD -- PD -- -- -- -- -- -- -- -- -- -- -- -- SA -- -- -- -- -- -- -- -- -- 30h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 555h AAh 2AAh 55h 555h AAh 2AAh 55h 555h AAh 2AAh 55h 555h AAh 2AAh 55h 555h AAh 2AAh 55h BA BA B0h 30h -- -- -- -- 80h 555h AAh 2AAh 55h 555h 10h 80h 555h AAh 2AAh 55h -- -- 20h -- -- -- -- -- -- -- SGA+ WPH -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 555h AAh 2AAh 55h XXXh A0h PA PD *4 F0h BA 90h XXXh 4 XXXh 60h SGA+ 60h WPH 40h SD -- -- -- -- -- -- 1 3 4 4 6 (BA) 98h 55h -- -- -- 555h 555h -- 88h A0h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RD (0) -- -- -- -- -- -- -- -- -- -- 555h AAh 2AAh 55h 555h AAh 2AAh 55h 555h AAh 2AAh 55h 555h AAh 2AAh 55h 555h AAh 2AAh 55h (HRA) PD PA (HRBA) 90h XXXh 00h 555h 555h 555h 555h 555h 555h 555h 555h 60h OPBP 68h OPBP 48h XXXh 38h XX0h PD0 38h XX1h PD1 38h XX2h PD2 38h XX3h PD3 -- -- -- Password Program 4 555h AAh 2AAh 55h 555h AAh 2AAh 55h 555h AAh 2AAh 55h -- -- -- Password Unlock Password Verify 7 4 555h AAh 2AAh 55h 555h AAh 2AAh 55h 28h XX0h PD0 XX1h PD1 XX2h PD2 XX3h PD3 C8h PWA PWD -- -- -- -- -- -- (Continued) 9 MBM29QM12DH-60 (Continued) Seventh Second Bus Third Bus Fourth Bus Sixth Bus First Bus Fifth Bus Bus Bus Write Write Read/Write Write Write Write Cycle Write Write CyCycle Cycle Cycle Cycle Cycle Cycle cles Req' Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data d 6 555h AAh 2AAh 55h 555h 60h PL 68h PL 48h XXXh RD (0) -- -- Command Sequence Password Mode Locking Bit Program Persistent Protection Mode Locking Bit Program PPB Program PPB Verify All PPB Erase PPB Lock Bit Set PPB Lock Bit Verify DPB Write DPB Erase DPB Verify Legend: RA PA 6 555h AAh 2AAh 55h 555h 60h SPML 68h SPML 48h XXXh RD (0) -- -- 6 4 4 3 4 4 4 4 555h AAh 2AAh 55h 555h 60h 555h AAh 2AAh 55h SGA+ WP 68h RD (0) 60h -- RD (1) X1h X0h RD (0) RD SGA+ 48h XXXh (0) WP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- (BA) SGA+ 90h 555h WP WP -- SA SA SA SA 555h AAh 2AAh 55h 555h 60h 555h AAh 2AAh 55h 555h 78h 555h AAh 2AAh 55h (BA) 58h 555h RD SGA+ 40h XXXh (0) WP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 555h AAh 2AAh 55h 555h 48h 555h AAh 2AAh 55h 555h 48h 555h AAh 2AAh 55h (BA) 58h 555h = Address of the memory location to be read = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A22, A21, A20, A19, A18, A17, A16, A15, A14, A13 and A12 will uniquely select any sector. BA = Bank Address. Address setted by A22, A21, A20 will select Bank A, Bank B, Bank C and Bank D. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse. SGA = Sector group address to be protected. WPH = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 0, 0, 0, 1, 0) SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. HRA = Address of the HiddenROM area Word Mode : 000000h to 00007Fh HRBA = Bank Address of the HiddenROM area (A22 = A21 = A20 = VIL) RD (0) = Read Data bit. If programmed, DQ0 = 1, if erase, DQ0 = 0 RD (1) = Read Data bit. If programmed, DQ1 = 1, if erase, DQ1 = 0 OPBP = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 1, 1, 0, 1, 0) PWA/PWD = Password Address/Password Data PL = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 0, 1, 0, 1, 0) SPML = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 1, 0, 0, 1, 0) WP = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 0, 0, 0, 1, 0) 10 MBM29QM12DH-60 *1 : This command is valid during Fast Mode. *2 : This command is valid while RESET = VID. *3 : This command is valid during HiddenROM mode. *4 : The data "00h" is also acceptable. *5 : Command combinations not described in "MBM29QM12DH Command Definitions Table" in "s DEVICE BUS OPERATION" are illegal. Notes : * Address bits A22 to A11 = X = "H" or "L" for all address commands except for PA, SA, BA, SGA, OPBP PWA, PL, SPML, WP WPH. , , * Bus operations are defined in "MBM29QM12DH User Bus Operations Table" and "MBM29QM12DH Command Definitions Table" in "s DEVICE BUS OPERATION". * The system should generate the following address patterns: Word Mode : 555h or 2AAh to addresses A10 to A0 * Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. MBM29QM12DH Sector Group Protection Verify Autoselect Codes Table A7 A6 A5 A4 A3 A2 A1 A0 Code (HEX) Type A22 to A12 Manufacture's Code Device Code Extended Device Code*3 Sector Group Protection Extended Device Code (Indicator Bits) BA*2 BA*2 BA*2 VIL VIL VIL VIL VIL VIL VIL VIL VIL X X X X VIL X X X X VIL VIL VIL VIH VIH VIL VIL VIL VIH VIH VIL VIL VIL VIH VIH VIH VIL VIH VIL VIH VIL 04h 227Eh 2220h 2200h 01h*1 Sector Group VIL Addresses BA*2 VIL VIL VIL VIL VIL VIL VIH DQ7 - Factory Lock Bit 1 = Locked, 0 = Not Locked VIH DQ6 - Customer Lock Bit 1 = Locked, 0 = Not Locked *1 : Sector Group can be protected by "Sector Group Protection", "Extended Sector Group Protection", and "New Sector Protection(PPB Protection). Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2 : When VID is applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank address needs to be indicated when Autoselect mode is read out at command mode, because then it becomes possible to activate simultaneous operation. *3 : A read cycle at address (BA) 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended Device Codes, will be required. Therefore the system may continue reading out these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh. Extended Autoselect Code Table Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 04h 227Eh 2220h 2200h 01h 00h 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 Type Manufacturer's Code Device Code Extended Device Code PPB Protection PPB Unprotection 11 MBM29QM12DH-60 s FLEXIBLE SECTOR-ERASE ARCHITECTURE Sector Address Table (Bank A) Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Sector Address Bank Address A22 A21 A20 A19 A18 A17 A16 A15 0 0 0 00000 0 0 0 00000 0 0 0 00000 0 0 0 00000 0 0 0 00000 0 0 0 00000 0 0 0 00000 0 0 0 00000 0 0 0 00001 0 0 0 00010 0 0 0 00011 0 0 0 00100 0 0 0 00101 0 0 0 00110 0 0 0 00111 0 0 0 01000 0 0 0 01001 0 0 0 01010 0 0 0 01011 0 0 0 01100 0 0 0 01101 0 0 0 01110 0 0 0 01111 0 0 0 10000 0 0 0 10001 0 0 0 10010 0 0 0 10011 0 0 0 10100 0 0 0 10101 0 0 0 10110 0 0 0 10111 0 0 0 11000 0 0 0 11001 0 0 0 11010 0 0 0 11011 0 0 0 11100 0 0 0 11101 0 0 0 11110 0 0 0 11111 Sector Size A14 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X (Kwords) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 ( x 16) Address Range 000000h to 000FFFh 001000h to 001FFFh 002000h to 002FFFh 003000h to 003FFFh 004000h to 004FFFh 005000h to 005FFFh 006000h to 006FFFh 007000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh Bank A 12 MBM29QM12DH-60 Sector Address Table (Bank B) Sector Address Bank Sector SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 Bank Address A22 A21 A20 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 Sector Size ( x 16) Bank B Address Range A19 A18 A17 A16 A15 A14 A13 A12 (Kwords) 0 0 0 0 0XXX 32 100000h to 107FFFh 0 0 0 0 1XXX 32 108000h to 10FFFFh 0 0 0 1 0XXX 32 110000h to 117FFFh 0 0 0 1 1XXX 32 118000h to 11FFFFh 0 0 1 0 0XXX 32 120000h to 127FFFh 0 0 1 0 1XXX 32 128000h to 12FFFFh 0 0 1 1 0XXX 32 130000h to 137FFFh 0 0 1 1 1XXX 32 138000h to 13FFFFh 0 1 0 0 0XXX 32 140000h to 147FFFh 0 1 0 0 1XXX 32 148000h to 14FFFFh 0 1 0 1 0XXX 32 150000h to 157FFFh 0 1 0 1 1XXX 32 158000h to 15FFFFh 0 1 1 0 0XXX 32 160000h to 167FFFh 0 1 1 0 1XXX 32 168000h to 16FFFFh 0 1 1 1 0XXX 32 170000h to 177FFFh 0 1 1 1 1XXX 32 178000h to 17FFFFh 1 0 0 0 0XXX 32 180000h to 187FFFh 1 0 0 0 1XXX 32 188000h to 18FFFFh 1 0 0 1 0XXX 32 190000h to 197FFFh 1 0 0 1 1XXX 32 198000h to 19FFFFh 1 0 1 0 0XXX 32 1A0000h to 1A7FFFh 1 0 1 0 1XXX 32 1A8000h to 1AFFFFh 1 0 1 1 0XXX 32 1B0000h to 1B7FFFh 1 0 1 1 1XXX 32 1B8000h to 1BFFFFh 1 1 0 0 0XXX 32 1C0000h to 1C7FFFh 1 1 0 0 1XXX 32 1C8000h to 1CFFFFh 1 1 0 1 0XXX 32 1D0000h to 1D7FFFh 1 1 0 1 1XXX 32 1D8000h to 1DFFFFh 1 1 1 0 0XXX 32 1E0000h to 1E7FFFh 1 1 1 0 1XXX 32 1E8000h to 1EFFFFh 1 1 1 1 0XXX 32 1F0000h to 1F7FFFh 1 1 1 1 1XXX 32 1F8000h to 1FFFFFh 0 0 0 0 0XXX 32 200000h to 207FFFh 0 0 0 0 1XXX 32 208000h to 20FFFFh 0 0 0 1 0XXX 32 210000h to 217FFFh 0 0 0 1 1XXX 32 218000h to 21FFFFh 0 0 1 0 0XXX 32 220000h to 227FFFh 0 0 1 0 1XXX 32 228000h to 22FFFFh 0 0 1 1 0XXX 32 230000h to 237FFFh (Continued) 13 MBM29QM12DH-60 Sector Address Bank Sector SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 Bank Address A22 A21 A20 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 Sector Size ( x 16) Bank B Address Range A19 A18 A17 A16 A15 A14 A13 A12 (Kwords) 0 0 1 1 1XXX 32 238000h to 23FFFFh 0 1 0 0 0XXX 32 240000h to 247FFFh 0 1 0 0 1XXX 32 248000h to 24FFFFh 0 1 0 1 0XXX 32 250000h to 257FFFh 0 1 0 1 1XXX 32 258000h to 25FFFFh 0 1 1 0 0XXX 32 260000h to 267FFFh 0 1 1 0 1XXX 32 268000h to 26FFFFh 0 1 1 1 0XXX 32 270000h to 277FFFh 0 1 1 1 1XXX 32 278000h to 27FFFFh 1 0 0 0 0XXX 32 280000h to 287FFFh 1 0 0 0 1XXX 32 288000h to 28FFFFh 1 0 0 1 0XXX 32 290000h to 297FFFh 1 0 0 1 1XXX 32 298000h to 29FFFFh 1 0 1 0 0XXX 32 2A0000h to 2A7FFFh 1 0 1 0 1XXX 32 2A8000h to 2AFFFFh 1 0 1 1 0XXX 32 2B0000h to 2B7FFFh 1 0 1 1 1XXX 32 2B8000h to 2BFFFFh 1 1 0 0 0XXX 32 2C0000h to 2C7FFFh 1 1 0 0 1XXX 32 2C8000h to 2CFFFFh 1 1 0 1 0XXX 32 2D0000h to 2D7FFFh 1 1 0 1 1XXX 32 2D8000h to 2DFFFFh 1 1 1 0 0XXX 32 2E0000h to 2E7FFFh 1 1 1 0 1XXX 32 2E8000h to 2EFFFFh 1 1 1 1 0XXX 32 2F0000h to 2F7FFFh 1 1 1 1 1XXX 32 2F8000h to 2FFFFFh 0 0 0 0 0XXX 32 300000h to 307FFFh 0 0 0 0 1XXX 32 308000h to 30FFFFh 0 0 0 1 0XXX 32 310000h to 317FFFh 0 0 0 1 1XXX 32 318000h to 31FFFFh 0 0 1 0 0XXX 32 320000h to 327FFFh 0 0 1 0 1XXX 32 328000h to 32FFFFh 0 0 1 1 0XXX 32 330000h to 337FFFh 0 0 1 1 1XXX 32 338000h to 33FFFFh 0 1 0 0 0XXX 32 340000h to 347FFFh 0 1 0 0 1XXX 32 348000h to 34FFFFh 0 1 0 1 0XXX 32 350000h to 357FFFh 0 1 0 1 1XXX 32 358000h to 35FFFFh 0 1 1 0 0XXX 32 360000h to 367FFFh 0 1 1 0 1XXX 32 368000h to 36FFFFh (Continued) 14 MBM29QM12DH-60 (Continued) Sector Address Bank Sector SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 Bank Address A22 A21 A20 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 Sector Size (x 16) Bank B Address Range A19 A18 A17 A16 A15 A14 A13 A12 (Kwords) 0 1 1 1 0XXX 32 370000h to 377FFFh 0 1 1 1 1XXX 32 378000h to 37FFFFh 1 0 0 0 0XXX 32 380000h to 387FFFh 1 0 0 0 1XXX 32 388000h to 38FFFFh 1 0 0 1 0XXX 32 390000h to 397FFFh 1 0 0 1 1XXX 32 398000h to 39FFFFh 1 0 1 0 0XXX 32 3A0000h to 3A7FFFh 1 0 1 0 1XXX 32 3A8000h to 3AFFFFh 1 0 1 1 0XXX 32 3B0000h to 3B7FFFh 1 0 1 1 1XXX 32 3B8000h to 3BFFFFh 1 1 0 0 0XXX 32 3C0000h to 3C7FFFh 1 1 0 0 1XXX 32 3C8000h to 3CFFFFh 1 1 0 1 0XXX 32 3D0000h to 3D7FFFh 1 1 0 1 1XXX 32 3D8000h to 3DFFFFh 1 1 1 0 0XXX 32 3E0000h to 3E7FFFh 1 1 1 0 1XXX 32 3E8000h to 3EFFFFh 1 1 1 1 0XXX 32 3F0000h to 3F7FFFh 1 1 1 1 1XXX 32 3F8000h to 3FFFFFh 15 MBM29QM12DH-60 Sector Address Table (Bank C) Sector Address Bank Sector SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158 SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 Bank Address A22 A21 A20 A19 A18 A17 A16 A15 A14 1 0 0 00000X 1 0 0 00001X 1 0 0 00010X 1 0 0 00011X 1 0 0 00100X 1 0 0 00101X 1 0 0 00110X 1 0 0 00111X 1 0 0 01000X 1 0 0 01001X 1 0 0 01010X 1 0 0 01011X 1 0 0 01100X 1 0 0 01101X 1 0 0 01110X 1 0 0 01111X 1 0 0 10000X 1 0 0 10001X 1 0 0 10010X 1 0 0 10011X 1 0 0 10100X 1 0 0 10101X 1 0 0 10110X 1 0 0 10111X 1 0 0 11000X 1 0 0 11001X 1 0 0 11010X 1 0 0 11011X 1 0 0 11100X 1 0 0 11101X 1 0 0 11110X 1 0 0 11111X 1 0 1 00000X 1 0 1 00001X 1 0 1 00010X 1 0 1 00011X 1 0 1 00100X 1 0 1 00101X 1 0 1 00110X A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 (x 16) Address Range 400000h to 407FFFh 408000h to 40FFFFh 410000h to 417FFFh 418000h to 41FFFFh 420000h to 427FFFh 428000h to 42FFFFh 430000h to 437FFFh 438000h to 43FFFFh 440000h to 447FFFh 448000h to 44FFFFh 450000h to 457FFFh 458000h to 45FFFFh 460000h to 467FFFh 468000h to 46FFFFh 470000h to 477FFFh 478000h to 47FFFFh 480000h to 487FFFh 488000h to 48FFFFh 490000h to 497FFFh 498000h to 49FFFFh 4A0000h to 4A7FFFh 4A8000h to 4AFFFFh 4B0000h to 4B7FFFh 4B8000h to 4BFFFFh 4C0000h to 4C7FFFh 4C8000h to 4CFFFFh 4D0000h to 4D7FFFh 4D8000h to 4DFFFFh 4E0000h to 4E7FFFh 4E8000h to 4EFFFFh 4F0000h to 4F7FFFh 4F8000h to 4FFFFFh 500000h to 507FFFh 508000h to 50FFFFh 510000h to 517FFFh 518000h to 51FFFFh 520000h to 527FFFh 528000h to 52FFFFh 530000h to 537FFFh (Continued) Bank C 16 MBM29QM12DH-60 Sector Address Bank Sector SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 SA195 SA196 SA197 SA198 SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 Bank Address A22 A21 A20 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 A19 A18 A17 A16 A15 A14 00111X 01000X 01001X 01010X 01011X 01100X 01101X 01110X 01111X 10000X 10001X 10010X 10011X 10100X 10101X 10110X 10111X 11000X 11001X 11010X 11011X 11100X 11101X 11110X 11111X 00000X 00001X 00010X 00011X 00100X 00101X 00110X 00111X 01000X 01001X 01010X 01011X 01100X 01101X A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 (x 16) Address Range 538000h to 53FFFFh 540000h to 547FFFh 548000h to 54FFFFh 550000h to 557FFFh 558000h to 55FFFFh 560000h to 567FFFh 568000h to 56FFFFh 570000h to 577FFFh 578000h to 57FFFFh 580000h to 587FFFh 588000h to 58FFFFh 590000h to 597FFFh 598000h to 59FFFFh 5A0000h to 5A7FFFh 5A8000h to 5AFFFFh 5B0000h to 5B7FFFh 5B8000h to 5BFFFFh 5C0000h to 5C7FFFh 5C8000h to 5CFFFFh 5D0000h to 5D7FFFh 5D8000h to 5DFFFFh 5E0000h to 5E7FFFh 5E8000h to 5EFFFFh 5F0000h to 5F7FFFh 5F8000h to 5FFFFFh 600000h to 607FFFh 608000h to 60FFFFh 610000h to 617FFFh 618000h to 61FFFFh 620000h to 627FFFh 628000h to 62FFFFh 630000h to 637FFFh 638000h to 63FFFFh 640000h to 647FFFh 648000h to 64FFFFh 650000h to 657FFFh 658000h to 65FFFFh 660000h to 667FFFh 668000h to 66FFFFh (Continued) Bank C 17 MBM29QM12DH-60 (Continued) Bank Sector SA213 SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230 Sector Address Bank Address A22 A21 A20 A19 A18 A17 A16 1 1 0 0111 1 1 0 0111 1 1 0 1000 1 1 0 1000 1 1 0 1001 1 1 0 1001 1 1 0 1010 1 1 0 1010 1 1 0 1011 1 1 0 1011 1 1 0 1100 1 1 0 1100 1 1 0 1101 1 1 0 1101 1 1 0 1110 1 1 0 1110 1 1 0 1111 1 1 0 1111 Sector Size A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X A12 (Kwords) X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 (x 16) Address Range 670000h to 677FFFh 678000h to 67FFFFh 680000h to 687FFFh 688000h to 68FFFFh 690000h to 697FFFh 698000h to 69FFFFh 6A0000h to 6A7FFFh 6A8000h to 6AFFFFh 6B0000h to 6B7FFFh 6B8000h to 6BFFFFh 6C0000h to 6C7FFFh 6C8000h to 6CFFFFh 6D0000h to 6D7FFFh 6D8000h to 6DFFFFh 6E0000h to 6E7FFFh 6E8000h to 6EFFFFh 6F0000h to 6F7FFFh 6F8000h to 6FFFFFh Bank C 18 MBM29QM12DH-60 Sector Address Table (Bank D) Sector Address Bank Sector SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269 Bank Address A22 A21 A20 A19 A18 1 1 1 00 1 1 1 00 1 1 1 00 1 1 1 00 1 1 1 00 1 1 1 00 1 1 1 00 1 1 1 00 1 1 1 01 1 1 1 01 1 1 1 01 1 1 1 01 1 1 1 01 1 1 1 01 1 1 1 01 1 1 1 01 1 1 1 10 1 1 1 10 1 1 1 10 1 1 1 10 1 1 1 10 1 1 1 10 1 1 1 10 1 1 1 10 1 1 1 11 1 1 1 11 1 1 1 11 1 1 1 11 1 1 1 11 1 1 1 11 1 1 1 11 1 1 1 11 1 1 1 11 1 1 1 11 1 1 1 11 1 1 1 11 1 1 1 11 1 1 1 11 1 1 1 11 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 Sector Size A12 (Kwords) X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 X 32 0 4 1 4 0 4 1 4 0 4 1 4 0 4 1 4 (x 16) Address Range 700000h to 707FFFh 708000h to 70FFFFh 710000h to 717FFFh 718000h to 71FFFFh 720000h to 727FFFh 728000h to 72FFFFh 730000h to 737FFFh 738000h to 73FFFFh 740000h to 747FFFh 748000h to 74FFFFh 750000h to 757FFFh 758000h to 75FFFFh 760000h to 767FFFh 768000h to 76FFFFh 770000h to 777FFFh 778000h to 77FFFFh 780000h to 787FFFh 788000h to 78FFFFh 790000h to 797FFFh 798000h to 79FFFFh 7A0000h to 7A7FFFh 7A8000h to 7AFFFFh 7B0000h to 7B7FFFh 7B8000h to 7BFFFFh 7C0000h to 7C7FFFh 7C8000h to 7CFFFFh 7D0000h to 7D7FFFh 7D8000h to 7DFFFFh 7E0000h to 7E7FFFh 7E8000h to 7EFFFFh 7F0000h to 7F7FFFh 7F8000h to 7F8FFFh 7F9000h to 7F9FFFh 7FA000h to 7FAFFFh 7FB000h to 7FBFFFh 7FC000h to 7FCFFFh 7FD000h to 7FDFFFh 7FE000h to 7FEFFFh 7FF000h to 7FFFFFh Bank D 19 MBM29QM12DH-60 Sector Group Address Table Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 SGA25 SGA26 SGA27 A22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 A18 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 A17 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A16 0 0 0 0 0 0 0 0 0 1 1 X X X X X X X X X X X X X X X X X A15 0 0 0 0 0 0 0 0 1 0 1 X X X X X X X X X X X X X X X X X A14 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X A13 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X A12 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X Sectors SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA35 to SA38 SA39 to SA42 SA43 to SA46 SA47 to SA50 SA51 to SA54 SA55 to SA58 SA59 to SA62 SA63 to SA66 SA67 to SA70 SA71 to SA74 SA75 to SA78 (Continued) 20 MBM29QM12DH-60 Sector Group SGA28 SGA29 SGA30 SGA31 SGA32 SGA33 SGA34 SGA35 SGA36 SGA37 SGA38 SGA39 SGA40 SGA41 SGA42 SGA43 SGA44 SGA45 SGA46 SGA47 SGA48 SGA49 SGA50 SGA51 A22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 A21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 A20 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 A19 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 A18 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 A17 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A16 X X X X X X X X X X X X X X X X X X X X X X X X A15 X X X X X X X X X X X X X X X X X X X X X X X X A14 X X X X X X X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X Sectors SA79 to SA82 SA83 to SA86 SA87 to SA90 SA91 to SA94 SA95 to SA98 SA99 to SA102 SA103 to SA106 SA107 to SA110 SA111 to SA114 SA115 to SA118 SA119 to SA122 SA123 to SA126 SA127 to SA130 SA131 to SA134 SA135 to SA138 SA139 to SA142 SA143 to SA146 SA147 to SA150 SA151 to SA154 SA155 to SA158 SA159 to SA162 SA163 to SA166 SA167 to SA170 SA171 to SA174 (Continued) 21 MBM29QM12DH-60 (Continued) Sector Group SGA52 SGA53 SGA54 SGA55 SGA56 SGA57 SGA58 SGA59 SGA60 SGA61 SGA62 SGA63 SGA64 SGA65 SGA66 SGA67 SGA68 SGA69 SGA70 SGA71 SGA72 SGA73 SGA74 SGA75 SGA76 SGA77 SGA78 SGA79 SGA80 SGA81 SGA82 SGA83 A22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A21 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 A17 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 A16 X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 1 1 1 1 1 1 1 A15 X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 1 1 1 1 1 1 1 A14 X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 A13 X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 A12 X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 Sectors SA175 to SA178 SA179 to SA182 SA183 to SA186 SA187 to SA190 SA191 to SA194 SA195 to SA198 SA199 to SA202 SA203 to SA206 SA207 to SA210 SA211 to SA214 SA215 to SA218 SA219 to SA222 SA223 to SA226 SA227 to SA230 SA231 to SA234 SA235 to SA238 SA239 to SA242 SA243 to SA246 SA247 to SA250 SA251 to SA254 SA255 to SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269 22 MBM29QM12DH-60 Common Flash Memory Interface Code Table Description Query-unique ASCII string "QRY" Primary OEM Command Set 02h: AMD/FJ standard type Address for Primary Extended Table Alternate OEM Command Set (00h = not applicable) Address for Alternate OEM Extended Table VCC Min voltage (write/erase) DQ7 to DQ4: 1 V, DQ3 to DQ0: 100 mV VCC Max voltage (write/erase) DQ7 to DQ4: 1 V, DQ3 to DQ0: 100 mV VPP Min voltage VPP Max voltage Typical timeout per single byte/word write 2N s Typical timeout for Min size buffer write 2N s Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms Max timeout for byte/word write 2N times typical Max timeout for buffer write 2N times typical Max timeout per individual block erase 2N times typical Max timeout for full chip erase 2N times typical Device Size = 2N byte Flash Device Interface description 01h : x 16 Max number of byte in multi-byte write = 2N Number of Erase Block Regions within device Erase Block Region 1 Information A6 to A0 DQ15 to DQ0 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h 0027h 0036h 0000h 0000h 0004h 0000h 0009h 0000h 0005h 0000h 0004h 0000h 0018h 0001h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 00FDh 0000h 0000h 0001h 0007h 0000h 0020h 0000h Description Erase Block Region 4 Information A6 to A0 DQ15 to DQ0 39h 3Ah 3Bh 3Ch 40h 41h 42h 43h 44h 0000h 0000h 0000h 0000h 0050h 0052h 0049h 0031h 0033h Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock Ch = Required and 0.13 m technology Dh = Not Required and 0.13 m technology Erase Suspend 02h = To Read & Write Sector Protection 00h = Not Supported X = Number of sectors in per group Sector Temporary Unprotection 01h = Supported Sector Protection Algorithm Simultaneous Operation 00h = Not Supported, X = Total number of sectors in all Banks except Bank A Burst Mode Type 00h = Not Supported Page Mode Type 00h = Not Supported VACC (Acceleration) Supply Minimum 00h = Not Supported, DQ7 to DQ4: 1 V, DQ3 to DQ0: 100 mV VACC (Acceleration) Supply Maximum 00h = Not Supported, DQ7 to DQ4: 1 V, DQ3 to DQ0: 100 mV Boot Type Program Suspend 01h = Supported Bank Organization Bank A Region Information Bank B Region Information Bank C Region Information Bank D Region Information 45h 000Ch 46h 47h 48h 49h 4Ah 0002h 0001h 0001h 0007h 00E7h 4Bh 4Ch 4Dh 0000h 0002h 0085h 4Eh 4Fh 50h 57h 58h 59h 5Ah 5Bh 0095h 0001h 0001h 0004h 0027h 0060h 0060h 0027h Erase Block Region 2 Information Erase Block Region 3 Information 23 MBM29QM12DH-60 s FUNCTIONAL DESCRIPTION Simultaneous Operation The device features functions that enable reading of data from one memory bank while a program or erase operation is in progress in the other memory bank (simultaneous operation) , in addition to conventional features (read, program, erase, erase-suspend read, and erase-suspend program) . The bank can be selected by bank address (A22, A21, A20) with zero latency. The device consists of the following four banks : Bank A : 8 x 4 KW and 31 x 32 KW; Bank B : 96 x 32 KW; Bank C : 96 x 32 KW; Bank D : 8 x 4 KW and 31 x 32 KW. The device can execute simultaneous operations between Bank 1, a bank chosen from among the four banks, and Bank 2, a bank consisting of the three remaining banks. (See "FlexBankTM Architecture Table" in "s FUNCTIONAL DESCRIPTION".) This is what we call a "FlexBank", for example, the rest of banks B, C and D to let the system read while Bank A is in the process of program (or erase) operation. However, the different types of operations for the three banks are impossible, e.g. Bank A writing, Bank B erasing, and Bank C reading out. With this "FlexBank", as described in "Example of Virtual Banks Combination Table" in "s FUNCTIONAL DESCRIPTION", the system gets to select from four combinations of data volume for Bank 1 and Bank 2, which works well to meet the system requirement. The simultaneous operation cannot execute multi-function mode in the same bank. "Simultaneous Operation Table" in "s FUNCTIONAL DESCRIPTION" shows the possible combinations for simultaneous operation. (Refer to "Bank-to-Bank Read/Write Timing Diagram" in "s TIMING DIAGRAM".) FlexBankTM Architecture Table Bank Splits 1 2 3 4 Bank 1 Volume 16 Mbit 48 Mbit 48 Mbit 16 Mbit Combination Bank A Bank B Bank C Bank D Volume 112 Mbit 80 Mbit 80 Mbit 112 Mbit Bank 2 Combination Remainder (Bank B, C, D) Remainder (Bank A, C, D) Remainder (Bank A, B, D) Remainder (Bank A, B, C) Example of Virtual Banks Combination Table Bank 1 Bank Splits Volume Combination Bank 2 Sector Size 8 x 4 Kwords + 31 x 32 Kwords 16 x 4 Kwords + 62 x 32 Kwords Volume Combination 112 Mbits Bank B + Bank C + Bank D Bank B + Bank C Bank A + Bank C + Bank D Bank C + Bank D Sector Size 8 x 4 Kwords + 223 x 32 Kwords 1 16 Mbit Bank A 2 32 Mbit Bank A + Bank D 96 Mbits 192 x 32 Kwords 3 48 Mbit Bank B 96 x 32 Kwords 80 Mbits 16 x 4 Kwords + 158 x 32 Kwords 8 x 4 Kwords + 127 x 32 Kwords 4 64 Mbit Bank A + Bank B 8 x 4 Kwords + 127 x 32 Kwords 64 Mbits Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B, neither Bank A nor Bank B is read out (they would output the sequence flag once they were selected.) Meanwhile the system would get to read from either Bank C or Bank D. 24 MBM29QM12DH-60 Simultaneous Operation Table Case 1 2 3 4 5 6 7 Bank 1 Status Read mode Read mode Read mode Read mode Autoselect mode Program mode Erase mode Bank 2 Status Read mode Autoselect mode Program mode Erase mode Read mode Read mode Read mode Note : Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank consists of 4 banks, Bank A, Bank B, BankC and Bank D. Bank Address (BA) means to specify each of the Banks. Read Mode The device has two control functions which are required in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins. Address access time (tACC) is equal to delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins (assuming the addresses have been stable for at least tACC - tOE time) . When reading out data without changing addresses after powerup, it is necessary to input hardware reset or to change CE pin from "H" or "L" Page Mode Read The device is capable of fast page mode read. This mode provides faster read access speed by sequential access within a page. The Page size of the device is 8 words, within the appropriate Page being selected by the higher address bits A22 to A3 and the LSB bits A2 to A0 determining the specific word within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. The random or initial page access is equal to tACC and subsequent page read access (as long as the locations specified by the microprocessor fall within that Page) is equivalent to tPACC. Here again, CE selects the device and OE is the output control and should be used to gate data to the output pins if the device is selected. Fast page mode accesses are obtained by keeping A22 to A3 constant and changing A2 to A0 within that page. Standby Mode There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET input held at VCC 0.3 V. Under this condition the current consumed is less than 5 A Max. During Embedded Algorithm operation, VCC active current (ICC2) is required even if CE = "H". The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS 0.3 V (CE = "H" or "L") . Under this condition the current consumed is less than 5 A Max. Once the RESET pin is set high, the device requires tRH as a wake-up time for output to be valid for read access. During standby mode, the output is in the high impedance state, regardless of OE input. 25 MBM29QM12DH-60 Automatic Sleep Mode Automatic sleep mode works to restrain power consumption during read-out of device data. It can be useful in applications such as handy terminal, which requires low power consumption. To activate this mode, the device automatically switches itself to low power mode when the device addresses remain stable during access time of 150 ns. It is not necessary to control CE, WE and OE in this mode. In this mode the current consumed is typically 1 A (CMOS Level) . During simultaneous operation, VCC active current (ICC2) is required. Since the data are latched during this mode, the data are continuously read out. When the addresses are changed, the mode is automatically canceled and the device reads the data for changed addresses. Output Disable With the OE input at a logic high level (VIH) , output from the device is disabled. This will cause the output pins to be in a high impedance state. Autoselect The Autoselect mode allows the reading out of a binary code and identifies its manufacturer and type.It is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID on address pin A9. Three identifier bytes may then be sequenced from the device outputs by toggling addresses. All addresses are DON'T CARES except A7, A6, A5, A4, A3, A2, A1 and A0. (See "MBM29QM12DH User Bus Operations Table" and "MBM29QM12DH Command Definitions Table" in "s DEVICE BUS OPERATION".) The manufacturer and device codes may also be read via the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in "MBM29QM12DH Command Definitions Table" in "s DEVICE BUS OPERATION". (Refer to Autoselect Command section.) In the command Autoselect mode, the bank addresses BA;(A22, A21, A20) must point to a specific bank during the third write bus cycle of the Autoselect command. Then the Autoselect data will be read from that bank while array data can be read from the other bank. In WORD mode, a read cycle from address 00h returns the manufacturer's code (Fujitsu = 04h) . A read cycle at address 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended Device Codes will be required. Therefore the system may continue reading out these Extended Device Codes at addresses of 0Eh and 0Fh. (Refer to "MBM29QM12DH Sector Group Protection Verify Autoselect Codes Table" and "Extended Autoselect Code Table" in "s DEVICE BUS OPERATION" ) In the case of applying VID on A9, since both Bank 1 and Bank 2 enter Autoselect mode, simultanous operation cannot be executed. Write Device erasure and programming are accomplished via the command register. The contents of the register serve as input to the internal state machine. The state machine output dictates the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later, while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Accelerated Program Operation The device offers accelerated program operation which enables the programming in high speed. If the system asserts VACC to the WP/ACC pin, the device automatically enters the acceleration mode and the time required 26 MBM29QM12DH-60 for program operation will reduce to about 60%. This function is primarily intended to allow high speed program, so caution is needed as the sector group will temporarily be unprotected. The system would use a fast program command sequence when programming during acceleration mode. Set command to fast mode and reset command from fast mode are not necessary. When the device enters the acceleration mode, the device automatically set to fast mode. Therefore, the pressent sequence could be used for programming and detection of completion during acceleration mode. Removing VACC from the WP/ACC pin returns the device to normal operation. Do not remove VACC from WP/ ACC pin while programming. See "Accelerated Program Timing Diagram" in "s TIMING DIAGRAM". RESET Hardware Reset The device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least "tRP" in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode "tREADY" after the RESET pin is driven low. Furthermore, once the RESET pin goes high the device requires an additional "tRH" before it will allow read access. When the RESET pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal should be ignored during the RESET pulse. See "RESET, RY/BY Timing Diagram" in "s TIMING DIAGRAM" for the timing diagram. Refer to Temporary Sector Group Unprotection for additional functionality. Boot Block Sector Protection The write protection function provides a hardware method of protecting certain boot sectors without using VID. This function is one of two provided by the WP/ACC pin. If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two outermost 8K bytes on both ends of boot sectors (SA0, SA1, SA268, SA269) independently of whether those sectors are protected or unprotected using the method described in "Sector Group Protection". If the system asserts VIH on the WP/ACC pin, the device reverts to whether the two outermost 8K byte on both ends of boot sectors ware last set to be protected or unprotected. Sector group protection or unprotection for these four sectors depends on whether they ware last protected or unprotected using the method described in "Sector Group Protection". HiddenROM Region The HiddenROM feature provides a Flash memory region that the system may access through a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the HiddenROM region is protected, any further modification of that region becomes impossible. This ensures the security of the ESN once the product is shipped to the field. ONLY Program is possible in this area until it is protected. Once it is protected, it is impossible to unprotect, so please use this with caution. HiddenROM area is 128 words (64 words for factory and 64 words for customer) in length and is stored at the same address of the "outermost" 4 Kwords boot sector. The device occupies the address of the 000000h to 00007Fh. After the system has written the Enter HiddenROM command sequence, the system may read the HiddenROM region by using the addresses normally occupied by the boot sector (particular area of SA0). That is, the device sends all commands that would normally be sent to the boot sector to the HiddenROM region. This mode of operation continues until the system issues the Exit HiddenROM command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sector. HiddenROM area is devided into two regions, which are Factory Locked area and Customer Locked area. The Factory Locked area is 64 words (address: 000000h to 00003Fh) that is programmed and locked at Fujitsu. The Customer Locked area is also 64 words (address: 000040h to 00007Fh) that is programmed and locked at user. The Factory indicator Bit (DQ7) is used to indicate whether or not the Factory Locked area is locked when shipped from the factory. The Customer Indicator Bit (DQ6) is used to indicate whether or not the Customer Locked area is locked. The Factory Locked area can be programmed and protected at Fujitsu ONLY and is always protected 27 MBM29QM12DH-60 when shipped from the factory regardless of the conditon whether or not this area is programmed. Therefore this area has the Factory Indicator Bit (DQ7) permanently set to a "1". The Factory Locked area cannot be modified in any way. The Customer Locked area is shipped unprotected, allowing users to utilize that area in any manner they choose. The Customer Indicator Bit set to "0". Once the Customer Locked area is protected, the Customer Indicator Bit will be permanently set to "1". (3) Extended Sector Group Protection [Software Protection] In addition to normal sector group protection, the device has Extended Sector Group Protection as extended function. This function enables protection of the sector group by forcing VID on RESET pin and writes a command sequence. Unlike conventional procedures, it is not necessary to force VID and control timing for control pins. The only RESET pin requires VID for sector group protection in this mode. The extended sector group protection requires VID on RESET pin. With this condition the operation is initiated by writing the set-up command (60h) in the command register. Then the sector group addresses pins (A22, A21, A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A7, A6, A5, A4, A3, A2, A1, A0) = (0, 0, 0, 0, 0, 0, 1, 0) should be set to the sector group to be protected (setting VIL for the other addresses pins is recommended) , and an extended sector group protection command (60h) should be written. A sector group is typically protected in 250 s. To verify programming of the protection circuitry, the sector group addresses pins (A22, A21, A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A7, A6, A5, A4, A3, A2, A1, A0) = (0, 0, 0, 0, 0, 0, 1, 0) should be set a command (40h) should be written. Following the command write, a logical "1" at device output DQ0 will produce a protected sector in the read operation. If the output is logical "0", write the extended sector group protection command (60h) again. To terminate the operation, it is necessary to set RESET pin to VIH. (Refer to "Extended Sector Gropup Protection Timing Diagram" in "s TIMING DIAGRAM" and "Extended Sector Group Protection Algorithm" in "s FLOW CHART".) If Persistent Protection Bit Lock is set to "1", this mode is disabled. (4) New Sector Protection [Software Protection] A command sector protection method that replaces the old VID controlled protection method in future. However MBM29QM12DH support both VID protection and Persistent Sector Protection. Both Protect supported as a shift period. The persistent Sector Protection and the old VID controlled protection can go back each other until Persistent Protection Lock Bit is settled. a) Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is assigned to a maximum four sectors (see the sector address tables for specific sector protection groupings). All 4 K words boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. Note: If a PPB requires erasure, all of the sector PPBs must first be preprogrammed prior to PPB erasing. All PPBs erase in parallel, unlike programming where individual PPBs are programmable. It is the responsibility of the user to perform the preprogramming operation. Otherwise, an already erased sector PPBs has the potential of being over-erased. There is no hardware mechanism to prevent sector PPBs over-erasure. b) Dynamic Protection Bit (DPB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DPBs is "0". Each DPB is individually modifiable through the DPB Write Command. When the parts are first shipped, the PPBs are cleared, the DPBs are cleared, and PPB Lock is defaulted to power up in the cleared state - meaning the PPBs are changeable. When the device is first powered on the DPBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DPB related to that sector. For the sectors that have the PPBs cleared, the DPBs control whether or not the sector is protected or unprotected. By issuing the DPB Write/Erase command sequences, the DPBs will be set or cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DPBs maybe set or cleared as often as needed. 28 MBM29QM12DH-60 PPB vs DPB The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are Non-Volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PBB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to "1". Setting the PPB Lock disables all program and erase commands to the NonVolatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed e.g. to allow new system code to be downloaded. If no changes are needed then the boot code can set the PBB Lock to disable any further changes to the PBBs during system operation. The WP/ACC write protect pin adds a final level of hardware protection to the two outermost 4 Kwords sectors. When this pin is low it is not possible to change the contents of these two sectors. These sectors generally hold system boot code. So, the WP/ACC pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DPB Write command sequence is all that is necessary. The DPB write/erase command for the dynamic sectors switch the DPBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again will lock the PPBs, and the device operates normally again. Note: To achieve the best protection, it's recommended to execute the PPB lock bit set command early in the boot code, and protect the boot code by holding WP/ACC = VIL. DPB 0 1 0 1 0 1 0 1 PPB 0 0 1 1 0 0 1 1 PPB Lock 0 0 0 0 1 1 1 1 Sector State Unprotected--PPB and DPB are changeable Protected--PPB and DPB are changeable Protected--PPB and DPB are changeable Protected--PPB and DPB are changeable Unprotected--PPB is not changeable, DPB is changeable Protected--PPB is not changeable, DPB is changeable Protected--PPB is not changeable, DPB is changeable Protected--PPB is not changeable, DPB is changeable The above table contains all possible combinations of the DPB, PPB, and PPB lock relating to the status of the sector. In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PBB lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The DPB then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 s before the device returns to read mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 s after which the device returns to read mode without having erased the protected sector. The programming of the DPB, PPB, and PPB lock for a given sector can be verified by writing a DPB/PPB lock verify command to the device. 29 MBM29QM12DH-60 -DPB Status The programming of the DPB for a given sector can be verified by writing a DPB status verify command to the device. -PPB Status The programming of the PPB for a given sector can be verified by writing a PPB status verify command to the device. -PPB Lock Bit Status The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit status verify command to the device. c) Persistent Protection Bit Lock (PPB Lock) * PPB Locked * PPB Locked with Password A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted. All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method will be used. If the customer decides to continue using the Persistent Sector Protection method, they must set the Persistent Sector Protection Mode Locking Bit. This will permanently set the part to operate only using Persistent Sector Protection. If the customer decides to use the password method, they must set the Password Mode Locking Bit. This will permanently set the part to operate only using password sector protection. It is important to remember that setting either the Persistent Sector Protection Mode Locking Bit or the Password Mode Locking Bit permanently selects the protection mode. It is not possible to switch between the two methods once a locking bit has been set. It is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. This is so that it is not possible for a system program or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. The WP/ACC Hardware Protection feature is always available, independent of the software managed protection method chosen. A global volatile bit. When set to "1", the PPBs cannot be changed. When cleared ("0"), the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Locking Bit is set, which indicates the device is in Password Protection Mode, the PPB Lock Bit is also set after a hardware reset (RESET asserted) or a power-up reset. The ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit back to a "1". If the Password Mode Locking Bit is not set, indicating Persistent Sector Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Sector Protection Mode. 30 MBM29QM12DH-60 -Password and Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the password. Fujitsu recommends that the password be somehow correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: (1) It permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. (2) It also disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands (see "Password Verify Command"). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device. -Persistent Sector Protection Mode Locking Bit Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents programming of the password protection mode locking bit. This guarantees that a hacker could not place the device in password protection mode. (5) Temporary Sector Group Unprotection This feature allows temporary unprotection of previously protected sectors of the device in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage (VID). During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be protected again. While PPB Lock is set, this device cannot enter the Temporary Sector Unprotection mode. 31 MBM29QM12DH-60 s COMMAND DEFINITION Device operations are selected by writing specific address and data sequences into the command register. Some commands require Bank Address (BA) input. When command sequences are input into a bank reading, the commands have priority over the reading. "MBM29QM12DH Command Definitions Table" in "s DEVICE BUS OPERATION" shows the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Also the Program Suspend (B0h) and Program Resume (30h) commands are valid only while the Program operation is in progress. Moreover, Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Writing incorrect address and data values or writing them in the improper sequence will take the device into unknow state. Read/Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, the Read/ Reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. The device will automatically power-up in the Read/Reset state. In this case a command sequence is not required in order to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to AC Read Characteristics and Timing Diagram for the specific timing parameters. Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. Therefore, manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a higher voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. The Autoselect command sequence is initiated first by writing two unlock cycles. This is followed by a third write cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device codes can be read from the bank, and actual data from the memory cell can be read from another bank. The higher order address (A22, A21, A20) required for reading out the manufacture and device codes demands the bank address (BA) set at the third write cycle. Following the command write, in WORD mode, a read cycle from address (BA) 00h returns the manufacturer's code (Fujitsu = 04h) . And a read cycle at address (BA) 01h outputs device code. When 227Eh was output, this indicates that two additional codes, called Extended Device Codes will be required. Therefore the system may continue reading out these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh. Notice that the above applies to WORD mode. (Refer to "MBM29QM12DH Sector Group Protection Verify Autoselect Codes Table" and "Extended Autoselect Code Table" in "s DEVICE BUS OPERATION" ) The sector state (PPB protection or PPB unprotection) will be informed by address (BA) XX02h for x 16 . Scanning the sector group addresses (A22, A21, A20, A19, A18, A17, A16, A15, A14, A13, and A12) while(A7, A6, A5, A4, A3, A2, A1,A0) = (0, 0, 0, 0, 0, 0, 1, 0) will produce a logical "1" at device output DQ0 for a protected sector group. The programming verification should be performed by verifying sector group protection on the protected sector. (See "MBM29QM12DH User Bus Operations Table" and "MBM29QM12DH Command Definitions Table" in "s DEVICE BUS OPERATION".) The manufacture and device codes can be read from the selected bank. To read the manufacture and device codes and sector protection status from a non-selected bank, it is necessary to write the Read/Reset command sequence into the register. Autoselect command should then be written into the bank to be read. If the software (program code) for Autoselect command is stored in the Flash memory, the device and manufacture codes should be read from the other bank, which does not contain the software. 32 MBM29QM12DH-60 To terminate the operation, it is necessary to write the Read/Reset command sequence into the register. To execute the Autoselect command during the operation, Read/Reset command sequence must be written before the Autoselect command. Word Programming Command The device is programmed on a word-by-word basis. Programming is a four bus cycle operation. There are two "unlock" write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later, and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) starts programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The system can determine the status of the program operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed. The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see "Hardware Sequence Flags Table" in "s COMMAND DEFINITION"). Therefore, the device requires that a valid address to the device be supplied by the system in this particular instance. Hence, Data Polling must be performed at the memory location which is being programmed. If hardware reset occurs during the programming operation, the data being written is not guaranteed. Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from Read/Reset mode will show that the data is still "0". Only erase operations can convert from "0"s to "1"s. "Embedded EraseTM Algorithm" in "s FLOW CHART" illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations. Program Suspend/Resume Command The Program Suspend command allows the system to interrupt a program operation so that data can be read from any address. Writing the Program Suspend command (B0h) during the Embedded Program operation immediately suspends the programming. The Program Suspend command may also be issued during a programming operation while an erase is suspended. The bank addresses of sector being programmed should be set when writing the Program Suspend command. When the Program Suspend command is written during a programming process, the device halts the program operation within 1 s and updates the status bits. After the program operation has been suspended, the system can read data from any address. The data at program-suspended address is not valid. Normal read timing and command definitions apply. After the Program Resume command (30h) is written, the device reverts to programming. The bank addresses of sectors being suspended should be set when writing the Program Resume command. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. The system may also write the Autoselect command sequence when the device in the Program Suspend mode. The device allows reading Autoselect codes at the addresses within programming sectors, since the codes are not stored in the memory. When the device exits the Autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" for more information. The system must write the Program Resume command (address bits are "Bank Address") to exit from the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device has resumed programming. 33 MBM29QM12DH-60 Chip Erase Command Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence, the device will automatically program and verify the entire memory for an allzero data pattern prior to electrical erase (Preprogram function) . The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) or RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence, and terminates when the data on DQ7 is "1" (see Write Operation Status section), at which time the device returns to the read mode. Chip Erase Time; Sector Erase Time x All sectors + Chip Program Time (Preprogramming) "Embedded EraseTM Algorithm" in "s FLOW CHART" illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. Sector Erase Command Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of CE or WE, whichever happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE, whichever happens first. After time-out of "tTOW" from the rising edge of the last sector erase command, the sector erase operation begins. Multiple sectors may be erased concurrently by writing the six bus cycle operations on "MBM29QM12DH Command Definitions Table" in "s DEVICE BUS OPERATION". This sequence is followed by writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than "tTOW". Otherwise, that command will not be accepted and erasure will not start. It is recommended that processor interrupts be disabled during this time to guarantee such a condition. The interrupts can reoccur after the last Sector Erase command is written. A time-out of "tTOW" from the rising edge of last CE or WE, whichever happens first, will initiate the execution of the Sector Erase command (s) . If another falling edge of CE or WE, whichever happens first occurs within the "tTOW" time-out window, the timer is reset (monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer). Resetting the device once execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete (refer to Write Operation Status section for Sector Erase Timer operation). Loading the sector erase buffer may be done in any sequence and with any number of sectors. Sector erase does not require the user to program the device before erase. The device automatically programs all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function) . When erasing a sector, the rest remain unaffected. The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) or RY/BY. The sector erase begins after the "tTOW" time-out from the rising edge of CE or WE, whichever happens first, for the last sector erase command pulse and terminates when the data on DQ7 is "1" (see Write Operation Status section), at which time the device returns to the read mode. Data polling and Toggle Bit must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time = [Sector Erase Time + Sector Program Time (Preprogramming) ] x Number of Sector Erase In case of multiple sector erase across bank boundaries, a read from the bank (read-while-erase) to which sectors being erased belong cannot be performed. "Embedded EraseTM Algorithm" in "s FLOW CHART" illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. 34 MBM29QM12DH-60 Erase Suspend/Resume Command The Erase Suspend command allows the user to interrupt Sector Erase operation and then reads data from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. Writing the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command (30h) resumes the erase operation. The bank address of sector being erased or erase-suspended should be set when writing the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device takes a maximum of "tSPD" to suspend the erase operation. When the device has entered the erase-suspended mode, the RY/BY output pin will be at High-Z and the DQ7 bit will be at logic "1", and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode, except that the data must be read from sectors that have not been erase-suspended. Reading successively from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle (see the section on DQ2). After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, it is the same as programming in the regular Program mode, except that the data must be programmed to sectors that are not erase-suspended. Reading successively from the erase-suspended sector while the device is in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-suspended Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I (DQ6), which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address within bank being erase-suspended. To resume the operation of Sector Erase, the Resume command (30h) should be written to the bank being erase suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Extended Command (1) Fast Mode The device has a Fast Mode function. It dispenses with the initial two unclock cycles required in the standard program command sequence by writing the Fast Mode command into the command register. In this mode, the required bus cycle for programming consists of two bus cycles instead of four in standard program command. During the Fast mode, do not write any commands other than the Fast program/Fast mode reset command. The read operation is also executed after exiting from the fast mode. To exit from this mode, it is necessary to write Fast Mode Reset command into the command register. The first cycle must contain the bank address (see "Embedded Program Algorithm fot Fast Mode" in "s FLOW CHART") .The VCC active current is required even if CE = VIH during Fast Mode. (2) Fast Programming During the Fast Mode, programming can be executed with two bus cycle operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD) (see "Embedded Program Algorithm fot Fast Mode" in "s FLOW CHART") . (3) CFI (Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and the host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent and forward-and backward-compatible software support for the specified flash device families. Refer to CFI specification in detail. The operation is initiated by writing the query command (98h) into the command register. The bank address should be set when writing this command. Then the device information can be read from the bank, and data from the memory cell can be read from the another bank. The higher order address (A22, A21, A20) required for reading out the CFI Codes requires that the bank address (BA) be set at the write cycle. Following the command write, a read cycle from specific address retrieves device information. Please note that output data of upper byte (DQ15 to DQ8) is "0" . Refer to CFI code table ("Common Flash Memory Interface Code Table" ) in "s FLEXIBLE 35 MBM29QM12DH-60 SECTOR-ERASE ARCHITECTURE". To terminate operation, it is necessary to write the read/reset command sequence into the register. HiddenROM Entry Command The device has a HiddenROM area with One Time Protect function. This area is to enter the security code and to unable the change of the code once set. Programming is allowed in this area until it is protected. However, once it gets protected, it is impossible to unprotect. Therefore, extreme caution is required. The HiddenROM area is 128 words (64 words for factory and 64 words for customer). This area is normally the "outermost" 4 Kwords boot block area. Therefore, write the HiddenROM entry command sequence to enter the HiddenROM area. It is called HiddenROM mode when the HiddenROM area appears. Sectors other than the boot block area (SA0) can be read during HiddenROM mode. Read/program of the HiddenROM area is possible during HiddenROM mode. Write the HiddenROM reset command sequence to exit the HiddenROM mode. The bank address of the HiddenROM should be set on the third cycle of this reset command sequence. In HiddenROM mode, the simultaneous operation cannot be executed multi-function mode between the HiddenROM area and the Bank A. The following commands are unavailable when the HiddenROM is enabled. Issuing the following commands while the HiddenROM is enabled results in the command being ignored. 1. CFI 2. Set to Fast Mode 3. Fast Program 4. Reset from Fast Mode 5. Program and Sector Erase Suspend 6. Program and Sector Erase Resume The HiddenROM Entry command is allowed when the device is in either program or erase suspend modes. If the HiddenROM is enabled, the program or erase suspend command is ignored. This prevents resuming either programming or erasure on the HiddenROM if the overlayed sector was undergoing programming or erasure. It is the responsibility of the software to resume the program or erasure of a suspended program or erase after exiting the HiddenROM. HiddenROM Program Command To program the data to the HiddenROM area, write the HiddenROM program command sequence during HiddenROM mode. This command is the same as the program command in usual except to write the command during HiddenROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7 data polling, and DQ6 toggle bit. Need to pay attention to the address to be programmed. If the address other than the HiddenROM area is selected to program, data of the address will be changed. HiddenROM Protect Command The method to protect the HiddenROM is to apply high voltage (VID) to A9 and OE, set the sector address in the HiddenROM area and (A7, A6, A5, A4, A3, A2, A1, A0) = (0, 0, 0, 1, 1, 0, 1, 0), and apply the write pulse during the HiddenROM mode. To verify the protect circuit, apply high voltage (VID) to A9, specify (A7, A6, A5, A4, A3, A2, A1, A0) = (0, 0, 0, 1, 1, 0, 1, 0) and the sector address in the HiddenROM area, and read. When "1" appears on DQ0, the protect setting is completed. "0" will appear on DQ0 if it is not protected. Please apply write pulse agian. And the device has also HiddenROM protect command wirhout VID. See "MBM29QM12DH Command Definitions Table" in "s DEVICE BUS OPERATION". Other sector will be effected if the address other than those for HiddenROM area is selected for the sector address, so please be carefull. Once it is protected, protection can not be cancelled, so please pay the closest attention. 36 MBM29QM12DH-60 Password Program Command The Password Program Command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64-bits long. 4 Password Program commands are required to program the password. The user must enter the unlock cycle, password program command (38h) and the program address/data for each portion of the password when programming. There are no provisions for entering the 2cycle unlock cycle, the password program command, and all the password data. There is no special addressing order required for programming the password. Also, when the password is undergoing programming, Simultaneous Operation is disabled. Read operations to any memory location will return the programming status. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verification. The Password Program Command is only capable of programming "0"s. Programming a "1" after a cell is programmed as a "0" results in a time-out by the Embedded Program Algorithm with the cell remaining as a "0". The password is all F's when shipped from the factory. All 64-bit password combinations are valid as a password. Writing the HiddenROM Exit command returns the device back to normal operation. Password Verify Command The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device will always drive all F's onto the DQ data bus. Also, the device will not operate in Simultaneous Operation when the Password Verify command is executed. Only the password is returned regardless of the bank address. The lower two address bits (A1:A0) are valid during the Password Verify. Writing the HiddenROM Exit command returns the device back to normal operation. Password Protection Mode Locking Bit Program Command The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking Bit, which prevents further verifies or updates to the Password. Once programmed, the Password Protection Mode Locking Bit cannot be erased. Once the Password Protection Mode Locking Bit is programmed, the Presistent Sector Protection Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection mode. After issuing "PL/68h" at 4th bus cycle, the device requires approximately 150 s time out period for programming the Password Protection Mode Locking Bit. Then by writing "PL/48h" at 5th bus cycle, the device outputs verify data at DQ0. If DQ0 = 1 then Password Protection Mode Locking Bit is programmed. If not, then the user needs to repeat this program sequence from the 4th cycle of "PL/68h". Exiting the Password Protection Mode Locking Bit Program command is accomplished by writing the HiddenROM Exit command. Persistent Sector Protection Mode Locking Bit Program Command The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector Protection Mode Locking Bit, which prevents the Password Mode Locking Bit from ever being programmed. By disabling the program circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set. After issuing "SPML/68h" at 4th bus cycle, the device requires approximately 150 s time out period for programming the Persistent Protection Mode Locking Bit. Then by writing "SPML/48h" at 5th bus cycle, the device outputs verify data at DQ0. If DQ0 = 1 then Persistent Protection Mode Locking Bit is programmed. If not, then the user needs to repeat this program sequence from the 4th cycle of "SPML/68h". Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing the HiddenROM Exit command. PPB Lock Bit Set Command The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a power-on clear or the Password Unlock command is executed. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command is accomplished by writing the HiddenROM Exit command. 37 MBM29QM12DH-60 DPB Write(Erase) Command The DPB Write command is used to set or clear a DPB for a given sector. The high order address bits (A22 to A12) are issued at the same time as the code 01h or 00h on DQ7 to DQ0. All other DQ data bus pins are ignored during the data write cycle. The DPBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DPBs are cleared at power-up or hardware reset.Exiting the DPB Write command is accomplished by writing the HiddenROM Exit command. DPB verify command DPB verify command is uesed to verify the status of a DPB for given sector.Scanning the sector addresses (SA) will produce a logical "1" at the device output DQ0 for a protected sector. Otherwise the device will produce "0" at DQ0 for the sector which is not protected. Writing the HiddenROM Exit Command returns the device back to normal operation. PPB Lock Bit verify command PPB Lock Bit verify command is used to verify the status of a PPB Lock Bit. A logical "1" at the device output DQ1 indicates that the PPB Lock Bit is set. If PPB Lock Bit is not set, DQ1 will output "0". Writing the HiddenROM Exit Command returns the device back to normal operation. Password Unlock Command The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become accessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 s at a time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 2 s execution window for each portion of the unlock, the command will be ignored. The Password Unlock function is accomplished by writing Password Unlock command and data to the device to perform the clearing of the PPB Lock Bit. A0 and A1 are used to determine the 16 bit data quantity is used to match separated 16 bits. Writing the Password Unlock command is address order specific. In other words, the lowers address A1:A0 = 00, the next cycle command is to A1:A0 = 01, then to A1:A0 = 10, and finally to A1:A0 = 11. Writing out of sequence results in the Password Unlock not returning a match with the password and the PPB Lock Bit remains set. Once the Password Unlock command is entered, the RY/BY pin goes LOW indicating that the device is busy. Also, reading the Bank A results in the DQ6 pin toggling, indicating that the Password Unlock function is in progress. Reading the other bank returns actual array data. Approximately 2 s is required for each portion of the unlock. Once the first portion of the password unlock completes (RY/BY is not driven and DQ6 does not toggle when read), the next cycle is issued, only this time with the next part of the password. Seven cycles Password Unlock commands are required to successfully clear the PPB Lock Bit. As with the first Password Unlock command, the RY/BY signal goes LOW and reading the device results in the DQ6 pin toggling on successive read operations until complete. It is the responsibility of the microprocessor to keep track of the number of Password Unlock cycles, the order, and when to read the PPB Lock bit to confirm successful password unlock. Writing the HiddenROM Exit Command returns the device back to normal operation. PPB Program Command The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed (but is bulk erased with the other PPBs). The specific sector address (A22 to A12) are written at the same time as the program command 60h. If the PPB Lock Bit is set and the corresponding PPB is set for the sector, the PPB Program command will not execute and the command will time-out without programming the PPB. After issuing "SGA + WP/68h" at 4th bus cycle, the device requires approximately 150 s time out period for programming the PPB. Then by writing "SGA + WP/48h" at 5th bus cycle, the device outputs verify data at DQ0. If DQ0 = 1 then PPB is programmed. If not, then the user needs to repeat this program sequence from the 4th cycle of "SGA + WP/68h". The PPB Program command does not follow the Embedded Program algorithm. Writing the HiddenROM Exit Command returns the device back to normal operation. 38 MBM29QM12DH-60 All PPB Erase Command The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually erasing a specific PPB. Unlike the PPB program, no specific sector address is required. However, when the PPB erase command is written (60h), all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command will not execute and the command will time-out without erasing the PPBs. After issuing "WP/60h" at 4th bus cycle, the device requires approximately 1.5 ms time out period for programming the PPB. Then by writing "SGA + WP/40h" at 5th bus cycle, the device outputs verify data at DQ0. If DQ0 = 0 then PPB is successfully erased. If not, then the user needs to repeat this program sequence from the 4th cycle of "WP/60h". It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user attempts to erase a cleared PPB, over-erasure may occur making it difficult to program the PPB at a later time. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. Writing the HiddenROM Exit Command returns the device back to normal operation. Write Operation Status Detailed in "Hardware Sequence Flags Table" in "s COMMAND DEFINITION" are all the status flags which can determine the status of the bank for the current mode operation. The read operation from the bank which doesn't operate Embedded Algorithm returns data of memory cells. These bits offer a method for determining whether an Embedded Algorithm is properly completed. The information on DQ2 is address-sensitive. This means that if an address from an erasing sector is consecutively read, the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consecutively read. This allows users to determine which sectors are in erase and which are not. The status flag is not output from banks (non-busy banks) which do not execute Embedded Algorithms. For example, a bank (busy bank) is executing an Embedded Algorithm. When the read sequence is [1] < busy bank >, [2] < non-busy bank >, [3] < busy bank >, the DQ6 toggles in the case of [1] and [3]. In case of [2], the data of memory cells are output. In the erase-suspend read mode with the same read sequence, DQ6 will not be toggled in [1] and [3]. In the erase suspend read mode, DQ2 is toggled in [1] and [3]. In case of [2], the data of memory cell is output. Hardware Sequence Flags Table DQ7 DQ7 0 Data Data 1 Data DQ7 DQ7 0 DQ7 Status DQ6 Toggle Toggle Data Data 1 Data Toggle Toggle Toggle Toggle DQ5 0 0 Data Data 0 Data 0 1 1 1 DQ3 0 1 Data Data 0 Data 0 0 1 0 DQ2 1 Toggle*1 Data Data Toggle Data 1*2 1 N/A N/A Embedded Program Algorithm Embedded Erase Algorithm Program Suspend Read (Program Suspended Sector) Program Suspended Mode Program Suspend Read (Non-Program Suspended Sector) Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspended Mode (Non-Erase Suspended Sector) Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Exceeded Embedded Erase Algorithm Time Limits Erase Erase Suspend Program Suspended Mode (Non-Erase Suspended Sector) In Progress *1 : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. *2 : Reading from non-erase suspend sector address will indicate logic "1" at the DQ2 bit. 39 MBM29QM12DH-60 DQ7 Data Polling The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce a complement of data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce true data last written to DQ7. For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse sequences. During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an attempt to read device will produce a "1" on DQ7. The flowchart for Data Polling (DQ7) is shown in "Temporary Sector Group Unprotection Algorithm" in "s FLOW CHART". Data polling will also flag the entry into Erase Suspend. DQ7 will switch "0" to "1" at the start of the Erase Suspend mode. Please note that the address of an erasing sector must be applied in order to observe DQ7 in the Erase Suspend Mode. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six write pulse sequences. Data Polling must be performed at sector addresses of sectors being erased, not protected sectors. Otherwise the status may become invalid. If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 s, then that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on DQ7 is active for approximately 400 s, then the bank returns to read mode. Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that device is driving status information on DQ7 at one instant, and then that byte's valid data at the next instant. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if device has completed the Embedded Algorithm operation and DQ7 has a valid data, data outputs on DQ0 to DQ6 may still be invalid. The valid data on DQ0 to DQ7 will be read on successive read attempts. The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. (See "Hardware Sequence Flags Table" in "s COMMAND DEFINITION".) See "Data Polling during Embedded Algorithm Operation Timing Diagram" in "s TIMING DIAGRAM" for the Data Polling timing specifications and diagrams. DQ6 Toggle Bit I The device also features the "Toggle Bit I" as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the busy bank will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequences. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write pulse sequences. The Toggle Bit I is active during the sector time out. In programming, if the sector being written is protected, the toggle bit will toggle for about 1 s and then stop toggling with data unchanged. In erase, the device will erase all selected sectors except for protected ones. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 s and then drop back into read mode, having data kept remained. Either CE or OE toggling will cause DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause DQ6 to toggle. The system can use DQ6 to determine whether a sector is actively erased or is erase-suspended. When a bank is actively erased (that is, the Embedded Erase Algorithm is in progress) , DQ6 toggles. When a bank enters the Erase Suspend mode, DQ6 stops toggling. Successive read cycles during erase-suspend-program cause DQ6 to toggle. 40 MBM29QM12DH-60 To operate toggle bit function properly, CE or OE must be high when bank address is changed. See "Data Polling during Embedded Algorithm Operation Timing Diagram" in "s TIMING DIAGRAM" for the Toggle Bit I timing specifications and diagrams. DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under these conditions DQ5 will produce "1". This is a failure condition indicating that the program or erase cycle was not successfully completed. Data Polling is only operating function of the device under this condition. The CE circuit will partially power down device under these conditions (to approximately 2 mA) . The OE and WE pins will control the output disable functions as described in "MBM29QM12DH User Bus Operations Table" in "s DEVICE BUS OPERATION". The DQ5 failure condition may also appear if a user tries to program a non-blank location without pre-erase. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never reads valid data on DQ7 bit and DQ6 never stop toggling. Once the device has exceeded timing limits, the DQ5 bit will indicate a "1." Please note that this is not a device failure condition since the device was incorrectly used. If this occurs, reset device with the command sequence. DQ3 Sector Erase Timer After completion of the initial sector erase command sequence, sector erase time-out begins. DQ3 will remain low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates that a valid erase command has been written, DQ3 may be used to determine whether the sector erase timer window is still open. If DQ3 is high ("1") the internally controlled erase cycle has begun. If DQ3 is low ("0") , the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See "Hardware Sequence Flags Table" in "s COMMAND DEFINITION" : Hardware Sequence Flags. DQ2 Toggle Bit II This toggle bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the non-erase suspended sector will indicate a logic "1" at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows : For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also "Toggle Bit Status Table" in "s COMMAND DEFINITION" and "DQ2 vs. DQ6" in "s TIMING DIAGRAM". Furthermore DQ2 can also be used to determine which sector is being erased. At the erase mode, DQ2 toggles if this bit is read from an erasing sector. To operate toggle bit function properly, CE or OE must be high when bank address is changed. 41 MBM29QM12DH-60 Reading Toggle Bits 3DQ6/DQ2 Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7 to DQ0 on the following read cycle. However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5) . If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (Refer to "Toggle Bit Algorithm" in "s FLOW CHART".) Toggle Bit Status Table DQ7 DQ7 0 1 DQ7 Mode Program Erase Erase-Suspend Read (Erase-Suspended Sector) Erase-Suspend Program DQ6 Toggle Toggle 1 Toggle DQ2 1 Toggle* Toggle 1* * : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from the non erase suspend sector address will indicate logic "1" at the DQ2 bit. RY/BY Ready/Busy The device provides a RY/BY open-drain output pin as a way to indicate to the host system that Embedded Algorithms are either in progress or have been completed. If output is low, the device is busy with either a program or erase operation. If output is high, the device is ready to accept any read/write or erase operation. If the device is placed in an Erase Suspend mode, RY/BY output will be high. During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate a busy condition during RESET pulse. Refer to "RY/BY Timing Diagram during Program/Erase Operation Timing Diagram" in "s TIMING DIAGRAM" and "RESET, RY/BY Timing Diagram" in "s TIMING DIAGRAM" for a detailed timing diagram. The RY/BY pin is pulled high in standby mode. Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC. Data Protection The device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power-up, the device automatically resets the internal state machine in Read mode. Also, with its control register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transitions or system noise. 42 MBM29QM12DH-60 Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO (Min) . If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the user's responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO (Min) . If the Embedded Erase Algorithm is interrupted, the intervened erasing sector (s) is (are) not valid. Write Pulse "Glitch" Protection Noise pulses of less than 3 ns (typical) on OE, CE or WE will not initiate a write cycle. Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. Power-Up Write Inhibit Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up. 43 MBM29QM12DH-60 s ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except A9, OE, and RESET *1,*2 Power Supply Voltage *1 A9, OE, and RESET *1,*3 WP/ACC * * 1, 4 Symbol Tstg TA VIN, VOUT VCC VIN VACC Rating Min -55 -40 -0.5 -0.5 -0.5 -0.5 Max +125 +85 VCC + 0.5 +4.0 +13.0 +10.5 Unit C C V V V V *1 : Voltage is defined on the basis of VSS = GND = 0 V. *2 : Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC+0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC+2.0 V for periods of up to 20 ns. *3 : Minimum DC input voltage on A9, OE and RESET pins is -0.5 V. During voltage transitions, A9, OE and RESET pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN - VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE and RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. *4 : Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0 V for periods of up to 20 ns when Vcc is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. s RECOMMENDED OPERATING CONDITIONS Parameter Ambient Temperature Power Supply Voltage VCCQ Supply Voltage* Symbol TA VCC VCCQ Part No. MBM29QM12DH 60/70 MBM29QM12DH 60/70 MBM29QM12DH 60 MBM29QM12DH 70 Value Min -40 +2.7 +2.7 +1.65 Max +85 +3.6 +VCC +1.95 Unit C V V V * : Voltage is defined on the basis of VSS = GND = 0 V. Note : Operating ranges define those limits between which the proper device function is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating conditionranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 44 MBM29QM12DH-60 s MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT +0.8 V -0.5 V -2.0 V 20 ns 20 ns 20 ns Maximum Undershoot Waveform VCC +2.0 V VCC +0.5 V 20 ns +2.0 V 20 ns 20 ns Maximum Overshoot Waveform 1 +14.0 V +13.0 V VCC +0.5 V 20 ns 20 ns 20 ns Note: This waveform is applicable for A9, OE, and RESET. Maximum Overshoot Waveform 2 45 MBM29QM12DH-60 s DC CHARACTERISTICS 1. DC Characteristics (VCCQ = 2.7 V to 3.6 V or 1.65 V to 1.95 V) Parameter Input Leakage Current Output Leakage Current A9, OE, RESET Inputs Leakage Current WP/ACC Accelerated Program Current Sym bol ILI ILO ILIT ILIA Conditions VIN = VSSQ to VCCQ, VCC = VCC Max VOUT = VSSQ to VCCQ, VCC = VCC Max VCC = VCC Max, A9, OE, RESET = 12.5 V VCC = VCC Max, WP/ACC = VACC Max CE = VIL, OE = VIH, f = 10 MHz CE = VIL, OE = VIH, f = 5 MHz CE = VIL, OE = VIH VCC = VCC Max, CE = VCCQ 0.3 V, RESET = VCCQ 0.3 V,WP/ACC = VCCQ 0.3 V VCC = VCC Max, RESET = VSSQ 0.3 V VCC = VCC Max, CE = VSSQ 0.3 V, RESET = VCCQ 0.3 V, VIN = VCCQ 0.3 V or VSSQ 0.3 V CE = VIL, OE = VIH CE = VIL, OE = VIH CE = VIL, OE = VIH CE = VIL, OE = VIH, 8 Words Read VCC = 2.7 V to 3.1 V VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.1 V VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.1 V VCC = 2.7 V to 3.6 V Value Min -1.0 -1.0 -0.5 0.7 x VCCQ 11.5 Typ 1 1 1 12 Max +1.0 +1.0 +35 20 45 60 25 30 25 5 5 5 45 45 25 10 15 VCCQ x 0.3 VCCQ+0.3 12.5 Un it A A A mA mA mA mA A A A mA mA mA mA V V V VCC Active Current * 1 ICC1 VCC Active Current *2 VCC Current (Standby) VCC Current (Standby, Reset) VCC Power Supply Current (Automatic Sleep Mode) *3 VCC Active Current *5 (Read-While-Program) VCC Active Current *5 (Read-While-Erase) VCC Active Current (Erase-Suspend-Program) VCC Active Current (Page Mode Read) Input Low Level Input High Level Voltage for Autoselect and Sector Protection (A9, OE, RESET) *4 Voltage for WP/ACC Sector Protection/Unprotection and Program Acceleration *4 Output Low Voltage Level Output High Voltage Level Low VCC Lock-Out Voltage ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICC8 ICC9 VIL VIH VID VACC VOL IOL = 100 A, VCC = VCC Min 8.5 0.85 x VCCQ 9.0 2.4 9.5 0.15 x VCCQ 2.5 V V V V VOH2 IOH = -100 A VLKO 2.3 *1: The ICC current listed includes both the DC operating current and the frequency dependent component. *2: ICC active while Embedded Algorithm (program or erase) is in progress. *3: Automatic sleep mode enables the low power mode when address remain stable for 150 ns. *4: Applicable for only VCC. *5: Embedded Algorithm (program or erase) is in progress. (@5 MHz) 46 MBM29QM12DH-60 s AC CHARACTERISTICS * Read Only Operations Characteristics Value Symbol Parameter JEDEC Read Cycle Time Address to Output Delay Page Read Cycle Time Page Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Address, CE or OE, Whichever Occurs First tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Standard tRC tACC tPRC tPACC tCE tOE tDF tDF tOH CE = VIL OE = VIL CE = VIL OE = VIL OE = VIL Test Setup VCCQ = 2.7 V to 3.6 V *1 Min 60 20 5 Max 60 20 60 20 20 20 VCCQ = 1.65 V to 1.95 V *2 Min 70 30 5 Max 70 30 70 30 30 30 ns ns ns ns ns ns ns ns ns Unit *1 : Test Conditions: Output Load: 1 TTL gate and 30 pF (Figure 4.1) Input rise and fall times: 5 ns Input pulse levels: 0.0 V or VCCQ Timing measurement reference level Input: 0.5 x VCCQ Output:0.5 x VCCQ *2 : Test Conditions: Output Load: CL = 30 pF (Figure 4.2) Input rise and fall times: 5 ns Input pulse levels: 0.0 V or VCCQ Timing measurement reference level Input: 0.5 x VCCQ Output:0.5 x VCCQ 3.3 V Diode = 1N3064 or equivalent Device Under Test 6.2 k CL Diode = 1N3064 or equivalent 2.7 k Device Under Test CL Figure 4.1 Test Conditions Figure 4.2 Test Conditions 47 MBM29QM12DH-60 * Write (Erase/Program) Operations Value Parameter Symbol JEDEC Write Cycle Time Address Setup Time Address Setup Time to OE Low during Toggle Bit Polling Address Hold Time Address Hold Time from CE or OE High during Toggle Bit Polling Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Toggle and Data Polling tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 3 2 VCCQ = 2.7 V to 3.6 V *1 Max tWC tAS 60 0 15 30 0 25 0 0 0 6 0.5 VCCQ = 1.65 V to 1.95 V *2 Min 70 0 15 35 0 30 0 0 0 10 0 0 0 0 0 0 40 40 25 25 50 500 500 4 100 4 4 Typ 6 0.5 Max Unit Standard Min Typ ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s ns ns s s s s tASO tAH tAHT tDS tDH tOES tOEH tGHWL tGHEL tCS tWS tCH tWH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVIDR tVACCR tVLHT tWPP tOESP tCSP 10 0 0 0 0 0 0 35 35 20 20 50 500 500 4 100 4 4 Read Recover Time Before Write Read Recover Time Before Write (OE High to CE Low) CE Setup Time WE Setup Time CE Hold Time WE Hold Time Write Pulse Width CE Pulse Width Write Pulse Width High CE Pulse Width High Word Programming Operation Sector Erase Operation*1 VCC Setup Time Rise Time to VID*2 Rise Time to VACC* Voltage Transition Time* Write Pulse Width* 2 2 2 OE Setup Time to WE Active* CE Setup Time to WE Active* (Continued) 48 MBM29QM12DH-60 (Continued) Value Parameter Symbol JEDEC Recover Time from RY/BY RESET Pulse Width RESET High Level Period Before Read Program/Erase Valid to RY/BY Delay Delay Time from Embedded Output Enable Sector Erase Time-out Period Erase Suspend Transition Time *2: This timing is for Sector Protection operation. *3: This timing is for Accelerated Program operation. -- -- -- -- -- -- -- VCCQ = 2.7 V to 3.6 V *1 VCCQ = 1.65 V to 1.95 V *2 Min 0 500 50 -- -- 50 -- Typ -- -- -- -- -- -- -- Max -- -- -- 90 70 -- 20 ns ns ns ns ns s s Unit Standard Min Typ Max tRB tRP tRH tBUSY tEOE tTOW tSPD 0 500 50 -- -- 50 -- -- -- -- -- -- -- -- -- -- -- 90 60 -- 20 *1: This does not include the preprogramming time. 49 MBM29QM12DH-60 s ERASE AND PROGRAMMING PERFORMANCE Limits Parameter Min Sector Erase Time Word Programming Time Chip Programming Time Erase/Program Cycle 100,000 Typ 0.5 6.0 50.3 Max 2 100 200 s s s cycle Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead Unit Comments Note : Typical Erase conditions TA = +25C, VCC = 2.9 V Typical Program conditions TA = +25C, VCC = 2.9 V, Data = checker s TSOP(1) PIN CAPACITANCE (TA = +25C, f = 1.0 MHz) Value Parameter Input Pin Capacitance Output Pin Capacitance Control Pin Capacitance Control Pin Capacitance (WP/ACC) Symbol CIN COUT CIN2 CIN3 Test Setup Typ VIN = 0 VOUT = 0 VIN = 0 VIN = 0 7 8 8 11 Max 10 12 11 12 pF pF pF pF Unit s FBGA PIN CAPACITANCE Value Parameter Input Pin Capacitance Output Pin Capacitance Control Pin Capacitance Control Pin Capacitance (WP/ACC) Symbol CIN COUT CIN2 CIN3 Test Setup Typ VIN = 0 VOUT = 0 VIN = 0 VIN = 0 7 8 8 11 Max 10 12 11 12 pF pF pF pF Unit 50 MBM29QM12DH-60 s TIMING DIAGRAM * Key to Switching Waveforms WAVEFORM INPUTS Must Be Steady May Change from H to L May Change from L to H "H" or "L": Any Change Permitted Does Not Apply OUTPUTS Will Be Steady Will Change from H to L Will Change from L to H Changing, State Unknown Center Line is HighImpedance "Off" State tRC Address tACC Address Stable CE tOE tDF OE tOEH WE tCE High-Z tOH High-Z Outputs Outputs Valid Read Operation Timing Diagram 51 MBM29QM12DH-60 A22 to A3 Same page Address A2 to A0 Aa tRC tACC tCE Ab tPRC Ac tPRC Ad tPRC Ae tPRC Af tPRC Ag tPRC Ah tPRC CE tOEH OE WE tOE tDF tPACC tOH tPACC tOH Db tPACC tOH Dc tPACC tOH Dd tPACC tOH De tPACC tOH Df tPACC tOH Dg tOH Dh Output High-Z Da Page Read Operation Timing Diagram tRC Address tACC Address Stable CE tRH tRP tRH tCE RESET tOH High-Z Outputs Outputs Valid Hardware Reset/Read Operation Timing Diagram 52 MBM29QM12DH-60 3rd Bus Cycle Data Polling PA tAS tAH PA tRC Address 555h tWC CE tCS tCH tCE OE tGHWL tWP tWPH tOE tWHWH1 WE tDS tDH tDF tOH Data A0h PD DQ7 DOUT DOUT Notes : * PA is address of the memory location to be programmed. * PD is data to be programmed at word address. * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates last two bus cycles out of four bus cycle sequence. Alternate WE Controlled Program Operation Timing Diagram 53 MBM29QM12DH-60 3rd Bus Cycle Data Polling PA tAS tAH PA Address 555h tWC WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CE tDS tDH PD DQ7 DOUT Data A0h Notes : * PA is address of the memory location to be programmed. * PD is data to be programmed at word address. * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates last two bus cycles out of four bus cycle sequence. Alternate CE Controlled Program Operation Timing Diagram 54 MBM29QM12DH-60 Address 555h tWC 2AAh tAS tAH 555h 555h 2AAh SA* CE tCS tCH OE tGHWL tWP tWPH WE tDS AAh tDH 55h 80h AAh 55h 10h for Chip Erase 10h/ 30h Data tVCS VCC * : SA is the sector address for Sector Erase. Addresses = 555h (at word mode) for Chip Erase. Chip/Sector Erase Operation Timing Diagram 55 MBM29QM12DH-60 CE tCH tOE tDF OE tOEH WE tCE * DQ7 = Valid Data DQ7 Data DQ7 High-Z tWHWH1 or 2 DQ6 to DQ0 Data tBUSY DQ6 to DQ0 = Output Flag tEOE DQ6 to DQ0 Valid Data High-Z RY/BY * : DQ7 = Valid Data (The device has completed the Embedded operation) . Data Polling during Embedded Algorithm Operation Timing Diagram 56 MBM29QM12DH-60 Address tAHT tASO tAHT tAS CE tCEPH WE tOEH tOEPH tOEH OE tDH tOE tCE DQ 6/DQ2 Data tBUSY Toggle Data Toggle Data Toggle Data * Stop Toggling Output Valid RY/BY Note : DQ6: Addresses are "Bank Address" where Embedded Algorithm is in progress. DQ2: Addresses are "Sector Address" where Embedded Algorithm (Erase) is in progress. * : DQ6 stops toggling (The device has completed the Embedded operation). AC Waveforms for Toggle Bit I during Embedded Algorithm Operations 57 MBM29QM12DH-60 Read tRC Command tWC Read tRC Command tWC Read tRC Read tRC Address BA1 tAS BA2 (555h) tAH BA1 tACC tCE BA2 (PA) BA1 tAS tAHT BA2 (PA) CE tOE tCEPH OE tGHWL tWP tOEH tDF WE tDS tDH tDF DQ Valid Output Valid Intput (A0h) Valid Output Valid Intput (PD) Valid Output Status Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1 : Address corresponding to Bank 1 BA2 : Address corresponding to Bank 2 Bank-to-Bank Read/Write Timing Diagram Enter Embedded Erasing Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete WE Erase Suspend Read DQ6 DQ2* Toggle DQ2 and DQ6 with OE or CE * : DQ2 is read from the erase-suspended sector. DQ2 vs. DQ6 58 MBM29QM12DH-60 CE Rising edge of the last WE signal WE Entire programming or erase operations RY/BY tBUSY RY/BY Timing Diagram during Program/Erase Operation Timing Diagram WE RESET tRP tRB RY/BY tREADY RESET, RY/BY Timing Diagram 59 MBM29QM12DH-60 A22, A21, A20 A19, A18, A17 A16, A15, A14 A13, A11 A7, A6, A5 A4, A3, A2 A0 SGAX SGAY A1 VID VIH A9 VID VIH OE tVLHT tVLHT tWPP tVLHT tVLHT WE tOESP CE tCSP Data tVCS tOE 01h VCC SGAX : Sector Group Address to be protected SGAY : Next Sector Group Address to be protected Sector Group Protection Timing Diagram 60 MBM29QM12DH-60 VCC tVCS tVIDR tVLHT VID VIH RESET CE WE tVLHT Program or Erase Command Sequence tVLHT RY/BY Unprotection period Temporary Sector Group Unprotection Timing Diagram 61 MBM29QM12DH-60 VCC tVCS RESET tVIDR tVLHT tWC tWC SGAX SGAX SGAY Address A7, A6, A5 A4, A3, A2 A0 A1 CE OE tWP TIME-OUT WE Data 60h 60h 40h tOE 01h 60h SGAX : Sector Group Address to be protected SGAY : Next Sector Group Address TIME-OUT : Time-Out window = 250 s (Min) Extended Sector Group Protection Timing Diagram 62 MBM29QM12DH-60 VCC tVCS tVACCR tVLHT VACC VIH WP/ACC CE WE tVLHT Program Command Sequence tVLHT RY/BY Acceleration period Accelerated Program Timing Diagram 63 MBM29QM12DH-60 s FLOW CHART Embedded AlgorithmTM Start Write Program Command Sequence (See Below) Data Polling Embedded Program Algorithm in program No Verify Data ? Yes Increment Address No Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 555h/AAh 2AAh/55h 555h/A0h Program Address/Program Data Embedded ProgramTM Algorithm 64 MBM29QM12DH-60 Embedded AlgorithmTM Start Write Erase Command Sequence (See Below) Data Polling Embedded Erase Algorithm in progress No Data = FFh ? Yes Erasure Completed Chip Erase Command Sequence (Address/Command): 555h/AAh Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 555h/AAh 2AAh/55h 2AAh/55h 555h/80h 555h/80h 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h Sector Address /30h Sector Address /30h Sector Address /30h 555h/10h Additional sector erase commands are optional. Embedded EraseTM Algorithm 65 MBM29QM12DH-60 Start Read (DQ7 to DQ0) Addr. = VA Yes VA = Address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = Any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation. DQ7 = Data? No No DQ5 = 1? Yes Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data? * No Fail Yes Pass * : DQ7 is rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5. Data Polling Algorithm 66 MBM29QM12DH-60 Start *1 Read DQ7 to DQ0 Addr. = VA Read DQ7 to DQ0 Addr. = VA *1 VA = Bank address being executed Embedded Algorithm. DQ6 = Toggle? Yes No DQ5 = 1? Yes No *1, 2 Read DQ7 to DQ0 Addr. = VA Read DQ7 to DQ0 Addr. = VA DQ6 = Toggle? Yes Program/Erase Operation Not Complete.Write Reset Command No Program/Erase Operation Complete *1 : Read toggle bit twice to determine whether it is toggling. *2 : Recheck toggle bit because it may stop toggling as DQ5 changes to "1". Toggle Bit Algorithm 67 MBM29QM12DH-60 Start 555h/AAh 2AAh/55h Set Fast Mode 555h/20h XXXh/A0h Program Address/Program Data In Fast Program Data Polling Verify Data? Yes Increment Address No Last Address? Yes Programming Completed No (BA) XXXh/90h Reset Fast Mode XXXh/F0h Embedded Programming Algorithm for Fast Mode 68 MBM29QM12DH-60 Start Setup Sector Group Addr. (A22, A21, A20, A19, A18, A17, A16, A15, A14, A13, A12) PLSCNT = 1 OE = VID, A9 = VID, CE = VIL, RESET = VIH A7 = A6 = A5 = A4 = A3 = A2 = A0 = VIL, A1 = VIH Activate WE Pulse Increment PLSCNT Time out 100 s WE = VIH, CE = OE = VIL (A9 should remain VID) Read from Sector (Addr. = SGA, A7 = A6 = A5 = A4 = A3 = A2 = A0 = VIL, A1 = VIH) No No PLSCNT = 25? Yes Remove VID from A9 Write Reset Command Data = 01h? Yes Yes Protect Another Sector Group? No Remove VID from A9 Write Reset Command Device Failed Sector Group Protection Completed Sector Group Protection Algorithm 69 MBM29QM12DH-60 Start RESET = VID *1 Perform Erase or Program Operations RESET = VIH Temporary Sector Group Unprotection Completed *2 *1 : All protected sector groups are unprotected. *2 : All previously protected sector groups are reprotected. Temporary Sector Group Unprotection Algorithm 70 MBM29QM12DH-60 Start RESET = VID Wait 4 s Device is Operating in Temporary Sector Group Unprotection Mode No First Write Cycle = 60h? Yes To Setup Sector Group Protection Write XXXh/60h PLSCNT = 1 To Protect Sector Group Write 60h to Sector Address A7 = A6 = A5 = A4 = A3 = A2 = A0 = VIL, A1 = VIH Time out 250 s To Verify Sector Group Protection Write 40h to Sector Address A7 = A6 = A5 = A4 = A3 = A2 = A0 = VIL, A1 = VIH ( ) Increment PLSCNT ( ) No Read from Sector Group Address (Addr. = SGA, A7 = A6 = A5 = A4 = A3 = A2 = A0 = VIL, A1 = VIH) No Data = 01h? Yes Protect Other Sector Group? No Remove VID from RESET Write Reset Command Setup Next Sector Group Address PLSCNT = 25? Yes Remove VID from RESET Write Reset Command Yes Device Failed Sector Group Protection Completed Extended Sector Group Protection Algorithm 71 MBM29QM12DH-60 Password Mode Choice Method Start Password Program Password Verify Password Protection Mode Bit Program No (Time out) DQ0 Yes Reset Command Reset Command Yes DQ0 = 1? No = 0? Reset Command Sector Protection Completed Password Sector Protect Algorithm 72 MBM29QM12DH-60 PPB Lock Clear in Password Mode Start Password Unlock Password Unlock No (Time out) RY/BY Yes No DPB/PPB/PPB Lock Bit Status DQ0 = H? = 1? Yes Reset Command Password/Unlock Complete All PPB Erase No (Time out) DQ0 Yes PPB Lock Bit Clear Completed Reset Command = 0? PPB Lock Bit Clear in Password Mode 73 MBM29QM12DH-60 s ORDERING INFORMATION Part No. MBM29QM12DH60PCN Package 56-pin plastic TSOP (1) (FPT-56P-M01) Normal Bend 80-pin plastic FBGA (BGA-80P-M04) Access Time (ns) 60 Remarks MBM29QM12DH60PBT 60 MBM29QM12D H 60 PCN PACKAGE TYPE PCN = 56-Pin Thin Small Outline Package (TSOP (1) Normal Bend) PBT = 80-Pin Fine Pitch Ball Grid Array Package (FBGA) SPEED OPTION See Product Selector Guide DEVICE REVISION DEVICE NUMBER/DESCRIPTION MBM29QM12D 128 Mbit (8M x 16-Bit) Page Mode Flash Memory 3.0 V-only, Page Mode and Dual Operation Flash Memory 74 MBM29QM12DH-60 s PACKAGE DIMENSIONS 56-pin plastic TSOP(1) (FPT-56P-M01) Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max) . Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. LEAD No. 1 56 0.100.05 (.004.002) (Stand off) INDEX 0.220.05 (.009.002) *1 14.000.10 (.551.004) 0.10(.004) M 0.50(.020) 28 29 Details of "A" part 20.000.20(.787.008) *2 18.400.10(.724.004) 0.170.03 .007.001 1.10 -0.05 +0.10 +.004 .043 -.002 (Mounting height) 0~8 0.600.15 (.024.006) 0.25(.010) 0.08(.003) "A" C 2002 FUJITSU LIMITED F56001S-c-4-5 Dimensions in mm (inches) . Note : The values in parentheses are reference values. (Continued) 75 MBM29QM12DH-60 (Continued) 80-pin plastic FBGA (BGA-80P-M04) +0.12 +.005 11.000.10(.433.004) 1.08 -0.13 .043 -.005 (Mounting height) B 0.40(.016) REF 0.80(.031) REF 0.380.10 (Stand off) (.015.004) A 8.000.10 (.315.004) 0.10(.004) S (INDEX AREA) S 8 7 6 5 4 3 2 1 MLKJHGFEDCBA (INDEX AREA) 80-o0.450.05 (80-o.018.002) 0.08(.003) M SAB C 2003 FUJITSU LIMITED B80004S-c-1-1 Dimensions in mm (inches) . Note : The values in parentheses are reference values. 76 MBM29QM12DH-60 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0407 (c) FUJITSU LIMITED Printed in Japan |
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